Shared Flash Translation Layer for Host-Device Coordination
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Solution Overview
Problem
Existing memory systems face challenges in achieving high I/O performance due to the complexity of controlling NAND flash memory, leading to inefficient role sharing between hosts and storage systems.
Innovation Solution
A memory system architecture where the role of the flash translation layer (FTL) is shared between the host and the flash storage device, with the host managing logical-to-physical address translation and the flash storage device handling low-level NAND flash memory operations, including garbage collection and data placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the host manages all NAND flash memory operations including FTL, then I/O performance can be optimized, but the host processing complexity and memory resource consumption increase
Solution Approach 1:
The patent divides the FTL functionality into two segments: host-side FTL for logical-to-physical address translation and storage management, and device-side FTL for low-level NAND flash control. This segmentation allows each component to manage only its specific tasks, reducing overall system complexity while maintaining performance optimization capabilities.
Solution Approach 2:
The patent introduces a shared FTL mechanism that acts as an intermediary between the host and the NAND flash memory. This shared FTL handles the complex address translation and data management tasks, allowing the host to interact with the storage system through simplified interfaces while the intermediary manages the underlying complexity.
2Ease of operation
If the storage device handles all low-level NAND flash operations, then the host needs only simple interfaces, but the storage device requires more sophisticated control mechanisms
Solution Approach 1:
The patent implements self-service mechanisms where the storage device autonomously manages its own FTL operations, garbage collection, and data placement. The device monitors its own state and performs necessary operations without constant host intervention, simplifying the host interface while managing device complexity internally.
Solution Approach 2:
The patent merges the FTL functionality between host and device into a coordinated shared system. Rather than completely separating controls, the system combines host-level address translation with device-level flash management through a shared FTL mechanism, achieving both interface simplicity and sophisticated control.
3Adaptability or versatility
If traditional FTL is implemented entirely in the host, then memory resources can be allocated flexibly, but write amplification increases and I/O performance decreases
Solution Approach 1:
The patent segments FTL responsibilities to reduce write amplification by handling data placement and garbage collection operations at the device level where they can be optimized for NAND flash characteristics. This segmentation allows the host to maintain flexible memory allocation while the device optimizes write operations for better performance.
Solution Approach 2:
The patent changes the operational parameters of FTL by implementing device-side control for data placement and garbage collection. This allows optimization of write operations based on actual NAND flash behavior, reducing write amplification and improving I/O performance while maintaining host-level flexibility through logical address space management.
4Productivity
If role sharing between host and storage is optimized, then I/O performance improves, but the system requires sophisticated coordination mechanisms
Solution Approach 1:
The patent implements feedback mechanisms where the storage device reports its operational status, available blocks, and garbage collection progress to the host. This feedback enables the host to adjust its commands accordingly, optimizing I/O performance through coordinated role sharing while managing coordination complexity through structured information exchange.
Solution Approach 2:
The patent creates a universal shared FTL mechanism that handles multiple functions including address translation, data placement, garbage collection coordination, and error management. This multi-functional approach simplifies the overall coordination by consolidating control logic while maintaining optimized I/O performance through unified management.
Data Source
AI summary
According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.