Shared FTL Memory Control for Lower Write Amplification
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Solution Overview
Problem
Existing memory systems with nonvolatile memories face challenges in managing complex control operations, leading to increased resource consumption, degraded I/O performance, and reduced SSD lifespan due to write amplification and noisy neighbor issues, particularly in systems with shared address translation and garbage collection responsibilities between hosts and storage devices.
Innovation Solution
A memory system architecture that shares the role of the Flash Translation Layer (FTL) between the host and the flash storage device, where the host manages logical-to-physical address translation and high-level functions like QoS control, while the storage device handles low-level operations such as garbage collection and conceals page-level details, thereby optimizing resource usage and reducing write amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the host manages all address translation and garbage collection functions, then control flexibility is improved, but host resource consumption and system complexity increase
Solution Approach 1:
The patent segments the FTL functionality into two parts: the host manages high-level functions (address translation, garbage collection scheduling) while the storage device handles low-level operations (page management, actual garbage collection execution). This segmentation distributes complexity appropriately, allowing the host to maintain control flexibility without being burdened by detailed memory management operations.
2Productivity
If garbage collection is performed frequently to maintain SSD performance, then I/O performance is improved, but write amplification increases and SSD lifespan decreases
Solution Approach 1:
The host performs preliminary address translation and identifies garbage collection candidates before the storage device executes garbage collection. By preparing the garbage collection task list in advance at the host level, the storage device can execute collections more efficiently with reduced overhead, minimizing the frequency and intensity of garbage collection operations while maintaining performance.
Solution Approach 2:
The system implements feedback mechanisms where the storage device reports its internal state (free block availability, wear level) to the host, which adjusts garbage collection scheduling accordingly. This feedback loop allows the system to perform garbage collection only when necessary, reducing write amplification while preventing performance degradation.
3Ease of operation
If the storage device conceals all page-level details from the host, then ease of use is improved, but the host loses ability to optimize resource usage
Solution Approach 1:
The patent creates a segmented information interface where the storage device conceals physical page details but exposes logical block information to the host. The host receives translated addresses and high-level status information sufficient for optimization decisions, while the storage device maintains concealment of implementation details. This segmentation allows both ease of use and optimized resource management.
Data Source
AI summary
According to one embodiment, a memory system. includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.