Shared Fuse Bus for Memory Row and Column Repair
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Solution Overview
Problem
Memory circuits face defects during fabrication, leading to faulty memory cells that impact chip yield, and existing solutions with redundant cells increase memory area and wiring complexity, necessitating a more efficient repair mechanism.
Innovation Solution
A memory circuit with a shared fuse bus for row and column repair, utilizing a controller, row repair decoder, and column repair decoder to map defective rows or columns to redundant rows or columns, allowing for flexible self-repair with minimal overhead by sharing repair information and pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant memory cells are added to increase repair coverage, then more defective cells can be repaired, but the memory cell area and wiring complexity increase
Solution Approach 1:
The patent merges the row repair and column repair functionality into a unified repair architecture. A single set of fuse pins and shared repair logic is used to handle both row and column repair operations, eliminating the need for separate redundant structures for each repair type. This consolidation achieves comprehensive repair coverage while minimizing the additional area required.
Solution Approach 2:
The repair decoder and fuse pins are designed with multi-functionality to serve dual purposes: row repair and column repair. The same hardware components can be configured to perform either type of repair based on the defect location, maximizing the utility of each redundant memory cell and reducing the overall area needed for repair functionality.
2Reliability
If redundant memory cells are added to increase repair coverage, then more defective cells can be repaired, but the wiring and pins required for repair signals increase
Solution Approach 1:
The patent combines the row repair and column repair signal paths into a single shared fuse bus. Instead of having separate fuse pins and wiring for row repair and column repair, the same fuse pins are used for both purposes by sharing the repair signal pathway. This significantly reduces the number of pins and wires required while maintaining full repair coverage for both row and column defects.
Solution Approach 2:
The fuse pins and repair decoder are designed as universal components that can handle both row and column repair operations. The repair decoder receives a single set of repair signals and dynamically configures itself to perform the appropriate repair type based on the defect location, eliminating the need for dedicated wiring for each repair mode.
3Reliability
If separate row repair and column repair structures are implemented, then both row and column defects can be repaired, but the device complexity and overhead increase
Solution Approach 1:
The patent merges separate row repair and column repair structures into a unified repair architecture. The row repair decoder and column repair decoder share common fuse pins, control logic, and repair memory resources. This consolidation maintains the ability to repair both row and column defects while significantly reducing the overall device complexity and overhead compared to having completely separate repair structures.
Solution Approach 2:
The repair structure is designed with universal components that can perform both row and column repair functions. The fuse pins and decoder logic are configured to handle either repair type as needed, creating a flexible, multi-functional repair system that reduces hardware overhead while maintaining comprehensive repair capability.
Data Source
AI summary
A self-repair memory circuit includes a cell array, a controller, a row repair decoder, and a column repair decoder. The cell array includes rows and columns of memory cells. The controller receives an input indicating row repair or column repair, and a repair address shared by the row repair and the column repair of the cell array. The row repair decoder maps the repair address of a defective row to a redundant row of the cell array when the input indicates the row repair. The column repair decoder maps the repair address of a defective column to another column of the cell array when the input indicates the column repair.