Shared Fuse Wrapper for Multi-Domain Memory Repair
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Solution Overview
Problem
Existing memory repair systems are limited to single power domains and cannot effectively support memories spanning multiple power domains, making them inefficient for complex semiconductor chip designs where multiple memories are prone to faults.
Innovation Solution
A Shared Fuse Wrapper architecture that uses a centralized fuse macro cell to store repair data for multiple memory blocks across various power domains, with parallel links and repair data registers to transmit and decode repair information, enabling memory repair across multiple power domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single fuse macro cell is used to store repair data for multiple memory blocks across multiple power domains, then chip area is reduced and resource utilization is improved, but the device complexity increases due to the need for shared architecture and parallel links
Solution Approach 1:
The patent merges multiple fuse macro cells into a single shared fuse macro cell that stores repair data for multiple memory blocks across multiple power domains. This consolidation reduces the total chip area occupied by fuse cells while maintaining the ability to repair all memory blocks through a centralized repair data storage location.
Solution Approach 2:
The shared fuse macro cell is designed to serve multiple functions simultaneously - it stores repair data for memory blocks in different power domains and supports repair operations for various memory types (SRAM, DDR, etc.). The universal design allows a single fuse cell to replace what would traditionally require multiple dedicated fuse cells.
2Adaptability or versatility
If repair data is centralized in a single fuse macro cell, then resource utilization is improved, but the difficulty of detecting and measuring repair data increases due to the need for parallel links and registers
Solution Approach 1:
The patent segments the repair data access path into multiple parallel links and individual repair data registers, each connected to specific memory blocks. This segmentation allows repair data to be distributed to multiple memory blocks simultaneously through separate parallel pathways, reducing the complexity of data access while maintaining centralized storage.
Solution Approach 2:
The patent introduces repair data registers as intermediary components between the centralized fuse macro cell and the multiple memory blocks. These registers act as buffers that hold repair data temporarily and facilitate its distribution to various memory blocks through parallel links, simplifying the detection and measurement processes.
3Adaptability or versatility
If multiple memory blocks span multiple power domains, then the system can support complex semiconductor chip designs, but the existing memory repair systems become inadequate and cannot effectively support repairs
Solution Approach 1:
The shared fuse macro cell is designed with universal capability to support repair operations across multiple power domains and various memory block types. This universal architecture ensures that the repair system remains effective and reliable regardless of the complexity of the memory configuration or the number of power domains involved.
Solution Approach 2:
The patent implements dynamic power domain management where power domains can be independently controlled and activated. During repair operations, only the necessary power domains are activated, allowing the system to adapt to different repair scenarios while maintaining reliability across complex multi-domain architectures.
Data Source
AI summary
A memory repair mechanism for the memories clustered across the multiple power domains and can be switched on and off independent of each other, thereby enabling low power operation. Enhancements in the shared Fuse Wrapper Architecture enable sharing of a plurality of parallel links connecting the memory blocks of each power domains to the Shared Fuse Wrapper architecture.