Shared Galois Field Engine for AES and CRC in Low-Power ICs
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Solution Overview
Problem
In ultra-low-power embedded systems, such as implantable biomedical devices, there is a need for secure and reliable data transmission that requires strong encryption and error checking, but existing solutions consume excessive power and area due to separate computational resources for Advanced Encryption Standard (AES) and Cyclic Redundancy Check (CRC) algorithms.
Innovation Solution
A low-power and area-efficient hardware engine is developed that shares resources to compute both AES and CRC algorithms using a single Galois Field Computation Unit (GFCU), decomposing operations into fundamental binary steps to identify arithmetic similarities and reduce active gates, enabling efficient multipurpose encryption processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate computational resources are used for AES and CRC algorithms, then security and reliability are ensured, but power consumption and area increase
Solution Approach 1:
The patent implements a universal Galois Field Computation Unit that can perform both AES encryption and CRC error checking operations. The same computational hardware is configured through control signals to execute different algorithms, eliminating the need for separate dedicated circuits for each function while maintaining both security and reliability requirements.
2Reliability
If separate computational resources are used for AES and CRC algorithms, then security and reliability are ensured, but integrated circuit layout area increases
Solution Approach 1:
The patent merges the AES and CRC computational resources into a single shared Galois Field Computation Unit. By combining what were previously separate hardware circuits into one unified structure, the integrated circuit layout area is reduced while both security (AES) and reliability (CRC) functions remain available through software-controlled configuration.
3Use of energy by moving object
If resource sharing is implemented for AES and CRC computation, then power consumption and area are reduced, but device complexity increases
Solution Approach 1:
The patent employs dynamic configuration where the Galois Field Computation Unit can switch between AES and CRC operations based on control signals. This dynamic approach allows a single hardware structure to perform multiple functions, reducing overall device complexity compared to having static separate circuits for each algorithm while maintaining low power consumption through selective activation.
Data Source
AI summary
For example, the present techniques may provide an energy-efficient multipurpose encryption engine capable of processing both AES and CRC algorithms using a shared Galois Field Computation Unit (GFCU). In an embodiment, an apparatus may comprise computation circuitry adapted to perform Galois Field computations and control circuitry adapted to control the computation circuitry so as to selectively compute either an Advanced Encryption Standard cipher or a Cyclic Redundancy Check.