Shared-Gate Control Logic for Dense 3D Memory Stacks
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Solution Overview
Problem
Semiconductor device designers face challenges in increasing packing density and reducing fabrication costs due to complications in electrical connection and sizing issues associated with 3D memory arrays, particularly in connecting memory cells across multiple decks, which are exacerbated by the complexity of routing and interconnect structures.
Innovation Solution
The implementation of a semiconductor device with a stack structure comprising multiple decks, each with a thin film transistor (TFT) control logic level, where CMOS devices share gate electrodes between transistors, facilitating efficient electrical communication and operation across decks, and utilizing a base control logic structure to manage operations across the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of decks in a 3D memory array is increased to improve storage density, then storage capacity increases, but the complexity of routing and interconnect structures increases, creating sizing and spacing complications
Solution Approach 1:
Multiple control logic devices share a common base control logic structure, merging control functions across different decks. This reduces the total quantity of control logic devices needed and simplifies routing by providing a centralized control point that manages multiple decks without requiring separate complex interconnect structures for each deck
Solution Approach 2:
The base control logic structure serves multiple decks simultaneously, making it a universal control unit. This multi-functional approach allows a single control logic assembly to manage operations across several decks, reducing the need for deck-specific control logic and simplifying the overall interconnect architecture
2Reliability
If the quantities and dimensions of routing and interconnect structures are increased to connect more decks, then electrical connection capability improves, but the size of the memory device increases and fabrication costs increase
Solution Approach 1:
Multiple decks are electrically connected to a shared base control logic structure rather than requiring dedicated connection structures for each deck. This merging of connection pathways reduces the total interconnect volume and device footprint while maintaining reliable electrical connections across all decks
Solution Approach 2:
The patent transitions from a two-dimensional planar interconnect architecture to a three-dimensional stacked architecture where control logic devices are positioned beneath multiple decks. This vertical arrangement allows electrical connections to be established through vertical vias and stacked configurations, reducing the lateral area required for interconnect structures
3Ease of manufacture
If conventional control logic devices are used without shared gate electrodes, then transistor control is simplified, but packing density is reduced due to larger device footprint
Solution Approach 1:
Adjacent transistors share common gate electrodes, merging what would otherwise be separate gate structures. This sharing reduces the total gate electrode volume and the space required for each individual transistor, thereby increasing packing density while maintaining the ability to control each transistor independently through selective gate voltage application
Solution Approach 2:
A single gate electrode structure serves multiple transistors simultaneously, making it a universal control element. This multi-functional gate electrode can control different transistors at different times or in combination, reducing the total number of gate electrodes needed and increasing device packing density
Data Source
AI summary
A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.