Shared-Gate Anti-Fuse Memory Structure for Higher Cell Density
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Solution Overview
Problem
The increasing density and shrinking size of semiconductor devices in integrated circuits pose a challenge for reducing the size of disposable anti-fuse programmable memory devices.
Innovation Solution
A semiconductor structure is designed with a substrate having a first doped region, a first isolation structure within the doped region, and gate structures that span the isolation structure, allowing two memory cells to share a single gate, thereby reducing the device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the density of devices in integrated circuits is increased, then the productivity and functionality are improved, but the size of semiconductor devices must be reduced which creates manufacturing and design challenges
Solution Approach 1:
The patent merges two memory cells into a single shared structure by having them share common components (gate electrode, isolation structure, doped region). This combining approach increases device density while managing the complexity of size reduction through shared resources rather than complete miniaturization of each individual cell.
Solution Approach 2:
The shared gate electrode and isolation structure serve multiple functions for both memory cells simultaneously. The gate electrode controls both memory cells, and the isolation structure provides electrical isolation for both cells, making these components universal rather than dedicated to a single cell, thereby improving density.
2Productivity
If the size of semiconductor devices is reduced, then the device density is improved, but the manufacturing precision and control become more difficult
Solution Approach 1:
By merging two memory cells into a shared structure with common gate and isolation components, the patent reduces the total area required while maintaining manufacturable dimensions for each shared component. The shared gate electrode and isolation structure can be fabricated with standard precision requirements rather than requiring extreme miniaturization.
Solution Approach 2:
The patent extends the isolation structure in the vertical direction (depth) rather than only reducing horizontal dimensions. The isolation structure has a depth greater than the doped region, providing effective electrical isolation while allowing horizontal dimensions to remain at manufacturable scales.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the formation of two semiconductor cells in a single semiconductor structure, effectively reducing the size of the semiconductor device while maintaining balanced data writing and reading rates.
Implementation Method 1
a first isolation structure, in which the first isolation structure is located in the first doped region
Implementation Method 2
After programming, the insulating dielectric layer is broken down, and the anti-fuse memory presents a low-resistance state
Data Source
AI summary
A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes: a substrate including a first doped region; a first isolation structure located in the first doped region, a depth of the first isolation structure being greater than that of the first doped region; a first gate structure located on the surface of the substrate of the first doped region and spanning the first isolation structure, a projection width of the first gate structure on the substrate being larger than that of the first isolation structure on the substrate; and second gate structures located on the surface of the substrate and at both sides of the first gate structure.