Shared Gate Cavity Void Prevention via Selective Metal Etching
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Solution Overview
Problem
As transistor gate lengths decrease, it becomes physically challenging to fit all layers of material in reduced-size gate cavities, leading to voids or seams in replacement gate structures, particularly in NMOS devices, which can result in substandard device performance or failure due to incomplete removal of work function metal layers during etching processes.
Innovation Solution
The method involves performing etching processes to remove sacrificial gate structures and form shared gate cavities across isolation regions, followed by selective removal of work function metal layers using masking layers to prevent voids and ensure complete removal, thereby forming final gate structures with controlled work function metal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length is reduced to increase transistor density, then device integration is improved, but voids or seams form in replacement gate structures during manufacturing
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before depositing gate materials. The mandrel serves as a pre-formed template that defines the gate cavity space, allowing subsequent gate materials to be deposited without forming voids or seams. This preliminary structural framework enables reduced gate lengths while maintaining gate structure integrity during manufacturing.
2Reliability
If multiple layers of material are deposited in reduced-size gate cavities, then high-k/metal gate structure formation is achieved, but voids or seams occur due to insufficient space
Solution Approach 1:
The patent implements the nested doll principle by placing multiple gate material layers within the gate cavity defined by the mandrel structure. The mandrel creates a nested configuration where high-k dielectric layers and metal gate layers are sequentially deposited within the confined space, ensuring continuous material layers without voids or seams while achieving the required high-k/metal gate structure.
3Adaptability or versatility
If work function metal layers are selectively removed using etching processes, then device-specific work function adjustment is achieved, but incomplete removal occurs leading to substandard device performance
Solution Approach 1:
The patent uses the mandrel structure as an intermediary element that facilitates selective removal of work function metal layers. The mandrel defines precise etch boundaries and protects adjacent regions during selective etching processes, ensuring complete and accurate removal of metal layers for NFET devices while preserving them for PFET devices, thereby achieving device-specific work function adjustment without incomplete removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reliable formation of replacement gate structures with reduced voids and seams, enhancing the operational performance of integrated circuit products by ensuring accurate material removal and preventing etchant flow through voids during the wet etching process.
Implementation Method 1
performing at least one etching process to remove a sacrificial gate structure for first and second transistor devices to thereby define a shared gate cavity
Implementation Method 2
forming a first masking layer that covers portions of the shared gate cavity positioned above the first and second active regions while exposing a portion of the shared gate cavity positioned above the isolation region
Implementation Method 3
performing at least one first etching process to remove at least a portion of the at least one layer of material in the exposed portion of the shared gate cavity above the isolation region
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, forming a shared gate cavity that spans across an isolation region and is positioned above first and second active regions, forming at least one layer of material in the shared gate cavity above the first and second active regions and above the isolation region, forming a first masking layer that covers portions of the shared gate cavity positioned above the first and second active regions while exposing a portion of the shared gate cavity positioned above the isolation region, with the first masking layer in position, performing at least one first etching process to remove at least a portion of the at least one layer of material in the exposed portion of the shared gate cavity above the isolation region, and removing the first masking layer.