Shared-Gate CMOS Structure With Isolated Regions Against Latchup
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Solution Overview
Problem
Latchup phenomenon in CMOS circuits, triggered by internal or external noise, leads to malfunction or electrical failure, particularly in aerospace, outer space, server, and automobile applications, due to single event latchup caused by particle strikes or electromagnetic radiation.
Innovation Solution
The semiconductor device configuration includes specific active areas and gate arrangements with metal contacts that manage voltage levels to reduce the number of parasitic SCR circuits, thereby minimizing high current leakage by routing currents through lower resistance paths and neutralizing currents within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors share gates in a CMOS circuit, then device complexity is reduced, but parasitic SCR circuits are formed causing latchup phenomena
Solution Approach 1:
The patent extracts and removes the harmful parasitic SCR circuits from the shared gate structure by introducing isolation mechanisms. Specifically, it separates the parasitic SCR paths from the functional gate structure, allowing the beneficial gate sharing while eliminating the harmful latchup phenomena through targeted removal of parasitic elements.
Solution Approach 2:
The patent introduces intermediary structures such as isolation regions and protective layers between the shared gates and active areas. These intermediaries act as mediators that prevent the formation of complete parasitic SCR circuits while maintaining the electrical functionality of the shared gate structure, thus resolving the contradiction between complexity reduction and parasitic elimination.
2Reliability
If parasitic SCR circuits are present, then current leakage increases causing malfunction, but removing them increases device complexity
Solution Approach 1:
The patent segments the device structure into distinct functional regions with different doping types and isolation characteristics. By dividing the CMOS circuit into separated n-type and p-type regions with appropriate isolation, it prevents the formation of complete parasitic SCR circuits while maintaining reasonable structural complexity through systematic segmentation rather than comprehensive redesign.
3Loss of energy
If metal contacts manage voltage levels to reduce parasitic SCR, then current leakage decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions during the fabrication process by pre-positioning metal contacts and pre-forming isolation structures before final device assembly. This preliminary positioning and formation of voltage-managing structures reduces current leakage pathways while allowing for standard manufacturing tolerances, thus reducing the precision requirements compared to post-fabrication adjustments.
Data Source
AI summary
A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.