Shared-Gate CMOS Transistor Structure With Fewer Parasitic SCR Paths
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Solution Overview
Problem
Latchup phenomenon in CMOS circuits, triggered by internal or external noise, leads to malfunction or electrical failure, particularly in aerospace, outer space, server, and automobile applications, due to single event latchup caused by particle strikes or electromagnetic radiation.
Innovation Solution
The semiconductor device configuration includes specific active areas and gate arrangements, with certain regions coupled to metal contacts and others disconnected, forming equivalent SCR circuits that reduce the number of parasitic SCR paths and redirect current flow through lower resistance paths, thereby minimizing high current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are arranged in a CMOS circuit with conventional gate structures, then the circuit functionality is achieved, but parasitic SCR paths are formed causing latchup phenomenon and high current leakage
Solution Approach 1:
The patent extracts and removes the harmful parasitic SCR paths from the CMOS circuit by selectively disconnecting drain regions from voltage supplies. Specifically, the second drain region is disconnected from the first voltage supply and the fourth drain region is disconnected from the second voltage supply, thereby eliminating the parasitic SCR conduction paths that cause latchup phenomenon while preserving the necessary circuit functionality.
Solution Approach 2:
The patent applies local quality by treating different drain regions differently within the same circuit. The first and third drain regions remain connected to their respective voltage supplies to maintain circuit operation, while the second and fourth drain regions are selectively disconnected to eliminate parasitic SCR paths. This localized differentiation allows the circuit to maintain functionality in critical areas while eliminating harmful effects in specific regions.
2Adaptability or versatility
If noise or particle strikes occur in the CMOS circuit, then the circuit operates normally under conventional structures, but latchup is triggered causing malfunction or electrical failure
Solution Approach 1:
The patent applies preliminary anti-action by proactively disconnecting certain drain regions from voltage supplies before latchup can be triggered by noise or particle strikes. By pre-configuring the circuit to disconnect the second drain region from the first voltage supply and the fourth drain region from the second voltage supply, the patent creates inherent immunity against latchup phenomenon, allowing the circuit to withstand external disturbances without malfunction.
3Productivity
If all drain regions are connected to voltage supplies to maintain circuit operation, then the circuit functions properly, but high current leakage occurs through parasitic SCR paths
Solution Approach 1:
The patent segments the drain regions into different functional groups with different connection states. The first and third drain regions are kept connected to voltage supplies to maintain circuit operation, while the second and fourth drain regions are disconnected to prevent current leakage. This segmentation allows the circuit to maintain productivity in essential areas while eliminating energy loss in specific regions where parasitic SCR paths would cause leakage.
Data Source
AI summary
A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.