Shared Gate Contact Layout for Dense Nanostructure FETs
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently, particularly in forming transistor gate contacts that maintain functionality and density without shorting or interference.
Innovation Solution
The formation of nanostructure-FETs with vertical nanostructures and shared gate contacts between adjacent transistors, utilizing gate structures wrapped around the sidewalls of semiconductor nanostructures, allows for improved integration density by eliminating the need for higher-level interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistor gate contacts are formed for each individual transistor, then each transistor can be properly controlled, but the integration density decreases and more interconnects are required
Solution Approach 1:
The patent merges multiple gate contacts into a single shared contact structure that serves multiple adjacent transistors. The gate contact is extended laterally to contact gate electrodes of multiple transistors simultaneously, eliminating the need for separate interconnects for each transistor and thereby increasing integration density.
Solution Approach 2:
The gate contact structure is designed to perform multiple functions by serving as the control input for multiple adjacent transistors. A single contact structure provides gate control to multiple gate electrodes, making the contact system universal rather than dedicated to individual transistors.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but the risk of shorting between adjacent structures increases
Solution Approach 1:
The patent introduces an intermediary dielectric material between adjacent gate contacts and transistor structures. This dielectric layer acts as a mediator that prevents direct electrical contact between adjacent structures, thereby reducing shorting risk while allowing reduced spacing for higher integration density.
Solution Approach 2:
The patent applies different material properties to different regions: conductive material for gate contacts where electrical connection is needed, and insulating dielectric material in regions where electrical isolation is required. This local differentiation of material quality enables dense integration while preventing shorts.
3Ease of operation
If more individual gate contacts are formed for each transistor, then each transistor can be independently controlled, but the manufacturing process becomes more complex
Solution Approach 1:
The patent combines multiple contact formation operations into a single manufacturing step. By forming one extended gate contact structure that serves multiple transistors, the process eliminates the need for multiple separate contact formation, patterning, and etching steps that would be required for individual contacts.
Solution Approach 2:
The gate contact structure is formed in advance to span multiple transistor regions, establishing a multi-functional contact before final transistor definition. This preliminary formation of an extended contact structure simplifies subsequent processing by eliminating the need for multiple individual contact fabrication steps.
Data Source
AI summary
In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.