Shared Transistor Gate Contacts Using Asymmetric Insulating Fins
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining device performance and integration density, particularly in sharing gate structures between transistors.
Innovation Solution
The formation of first and second insulating fins of different heights allows for a gate structure to extend over one fin but not the other, enabling shared gate structures between some transistors, particularly advantageous for static random-access memory (SRAM) cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate structures are shared between transistors to reduce interconnects, then device complexity is reduced, but short channel effects and leakage increase
Solution Approach 1:
The patent applies local quality by creating different fin heights in different regions of the semiconductor device. First fins have a first height while second fins have a second height greater than the first height. This allows the gate structure to selectively contact different fin regions, providing local electrical isolation where needed while maintaining shared gate structures in other areas, thus resolving the contradiction between reducing interconnect complexity and preventing leakage.
2Productivity
If minimum feature sizes are reduced to increase integration density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional structures by forming fins of different heights. This vertical dimensionality change allows for better electrical isolation and gate control without further reducing the lateral feature sizes, thereby maintaining manufacturing precision while achieving higher integration density through the added vertical dimension.
3Device complexity
If insulating fins of different heights are formed to enable shared gate structures, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the fin structure into multiple regions with different heights - first fins with a first height and second fins with a second height. This segmentation is achieved through selective epitaxial growth processes that can precisely control the height of different fin regions. The segmentation allows the gate structure to be shared between some transistors while maintaining electrical isolation where needed, reducing overall device complexity while using manufacturing processes capable of achieving the required height precision.
Data Source
AI summary
In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.