Shared-Control Gate Driver Layout for Lower Display Dead Space
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Solution Overview
Problem
The integration of a large number of transistors and signal lines in a gate driver within a display device leads to increased dead space and power consumption.
Innovation Solution
A gate driver design that includes a control circuit shared by multiple gate output circuits, reducing the number of transistors and signal lines per stage, thereby minimizing dead space and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of transistors and signal lines in the gate driver is increased, then the gate driver can control more gate lines, but the dead space and power consumption increase
Solution Approach 1:
Multiple gate output circuits share a common control circuit, merging the control functions into a single unified structure. This reduces the total number of transistors and signal lines required, thereby decreasing power consumption while maintaining the ability to control multiple gate lines through the shared control mechanism
Solution Approach 2:
The control circuit is designed to serve multiple gate output circuits simultaneously, making it a universal control unit. This multi-functional design allows the same control circuit to manage different gate lines, increasing adaptability without proportionally increasing the number of components
2Adaptability or versatility
If the number of transistors and signal lines in the gate driver is increased, then the gate driver can control more gate lines, but the dead space increases
Solution Approach 1:
By merging the control circuits into a single shared structure, the physical area occupied by the gate driver is reduced. This consolidation eliminates redundant components and interconnects, thereby minimizing dead space while preserving the capability to control multiple gate lines
Solution Approach 2:
The patent employs a time-multiplexed approach where the shared control circuit sequentially controls different gate output circuits at different time intervals. This temporal dimension allows multiple gate lines to be controlled without requiring separate physical control circuits for each, effectively reducing spatial requirements
Data Source
AI summary
A gate driver includes a plurality of stages. Each of the stages includes a control circuit and first to (M−1)-th gate output circuits, and each of the stages receives first to M-th clock signals, respectively, where M is a positive integer greater than or equal to 3. The control circuit receives an input signal in response to one of the first to M-th clock signals, and controls a voltage of a control node and a voltage of an inverted control node based on the input signal. The first to (M−1)-th gate output circuits sequentially outputs clock signals different from the one of the first to M-th clock signals received by the control circuit among the first to M-th clock signals as first to (M−1)-th gate signals in response to the voltage of the control node and the voltage of the inverted control node.