Shared-Gate GAA Logic Cell Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuits (ICs) while maintaining performance due to increased complexity and leakage current, particularly in gate-all-around (GAA) transistors, which require improved gate control and reduced parasitic capacitance.
Innovation Solution
The implementation of nanostructure transistors with vertically stacked sheets or wires in the channel region, combined with advanced patterning techniques like double-patterning or multi-patterning processes, allows for better gate control and reduced leakage current, and the arrangement of active regions under metal lines in logic cells minimizes parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices (FinFETs, MBC transistors) are used to improve gate control, then gate-channel coupling is improved and off-state current is reduced, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent transitions from planar 2D gate control to three-dimensional gate-all-around control by stacking nanostructures vertically. The gate structure completely surrounds the channel region in 3D space, providing superior electrostatic control compared to conventional FinFETs. This dimensional transition enables better gate-channel coupling while managing the inherent complexity through systematic fabrication processes.
2Productivity
If device size is decreased to increase functional density, then more devices fit per chip area, but short-channel effects increase and manufacturing precision requirements increase
Solution Approach 1:
The channel region is segmented into multiple discrete nanostructures (nanosheets, nanowires, or nanorods) stacked vertically. This segmentation allows each nanostructure to be independently formed and controlled, enabling precise fabrication at small dimensions. The segmented approach facilitates better manufacturing control while achieving high functional density through vertical stacking rather than lateral scaling.
3Ease of manufacture
If conventional planar transistors are used, then manufacturing is simpler, but gate control deteriorates and leakage current increases at small dimensions
Solution Approach 1:
The gate structure is nested around the channel region in a complete surround configuration, with the gate dielectric layer and gate electrode wrapping around all sides of the vertical nanostructure. This nested gate-all-around geometry provides comprehensive control over the channel, preventing leakage paths that plague planar devices at small dimensions, while the systematic fabrication process maintains manufacturing feasibility.
Data Source
AI summary
A semiconductor structure is provided. A logic cell includes first and second nanostructure transistors. The first nanostructure transistor is formed in a first active region over a first well region having a first conductivity type. The second nanostructure transistor is formed in a second active region over a second well region having a second conductivity type. The first and second nanostructure transistors share a gate structure. First and second source/drain features of the first nanostructure transistor are formed in the first active region. Third and fourth source/drain features of the second nanostructure transistor are formed in a first portion and a second portion of the second active region, respectively. A first distance between the first active region and the first portion of the second active region is different from a second distance between the first active region and the second portion of the second active region.