Shared-Gate Image Sensor Layout for Submicron Pixel Pitch
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Solution Overview
Problem
Image sensors with small-pixel layouts face manufacturing space constraints and high fabrication costs due to process variations and the need for additional masks and processing steps in stacked chip schemes, which hinders the development of high-performance image sensors with submicron pixel pitch.
Innovation Solution
A stacked chip scheme with a shared gate architecture that reduces metal layers by using polycrystalline silicon or other conductive materials for shared gate electrodes and threshold voltage implant areas, allowing for submicron pixel pitch while mitigating process variations and lowering fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional separate gate architecture is used, then manufacturing precision is maintained, but device complexity and fabrication cost increase due to additional metal layers and processing steps
Solution Approach 1:
The patent merges the gate electrode and threshold voltage implant area into a single shared structure. The gate electrode serves dual purposes: as the control electrode for the transistor and as the implant area for threshold voltage adjustment. This consolidation eliminates the need for separate metal layers and processing steps, reducing device complexity while maintaining manufacturing precision through unified structure formation.
Solution Approach 2:
The gate electrode is designed to perform multiple functions simultaneously: electrical control of the transistor channel and threshold voltage implantation target. By making the gate structure universal, the patent reduces the number of discrete components and metal layers required, simplifying the overall device architecture without compromising manufacturing control.
2Measurement precision
If pixel size is reduced for high resolution, then resolution improves, but manufacturing space constraints and fabrication cost increase
Solution Approach 1:
By combining the gate electrode and threshold voltage implant area into one structure, the patent reduces the lateral space required per transistor. This space savings enables smaller pixel pitch and higher resolution while maintaining ease of manufacture, as the shared structure requires fewer fabrication steps and less complex routing.
Solution Approach 2:
The patent segments the pixel layout by implementing shared gates that can serve multiple transistors within a pixel or across pixel boundaries. This segmentation approach allows for more efficient space utilization, enabling reduced pixel size without proportionally increasing fabrication complexity.
3Manufacturing precision
If additional metal layers are added for separate gate structures, then manufacturing precision is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent eliminates the need for additional metal layers by merging the gate electrode function with the threshold voltage implant area. The gate structure is formed as part of the semiconductor device fabrication process itself, using the same polysilicon or conductive material layers, thereby maintaining manufacturing precision without increasing metal layer count or device complexity.
Data Source
AI summary
An image sensor comprising a semiconductor substrate, a first source region, a second source region, and a shared gate electrode is described. The semiconductor substrate includes a first side and a second side opposite the first side. The first source region and the second source region are each disposed within the semiconductor substrate proximate to the first side. The first source region is separated from the second source region by an isolation structure disposed within the semiconductor substrate between the first source region and the second source region. The shared gate electrode is disposed proximate to the first side of the semiconductor substrate and coupled to the first source region and the second source region to respectively form a first transistor and a second transistor.