Shared Gate Electrode for LTPS and Oxide Transistors
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Solution Overview
Problem
Mainstream OLED displays driven by LTPS backplanes face issues with stress mismatch between film layers, leading to transistor failures due to excessive stacking, which increases the risk of cracks and reduces product yield.
Innovation Solution
A display substrate design incorporating both low temperature poly-silicon and oxide transistors on the same layer, with heavily-doped poly-silicon gate electrodes, reduces the number of stacked layers and eliminates the need for additional film layers, thereby minimizing stress-induced cracks and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple film layers are stacked to implement both LTPS TFT and Oxide TFT, then the display product can achieve high resolution and low power consumption, but the stress mismatch between film layers increases, leading to transistor failures and reduced product yield
Solution Approach 1:
The patent merges the gate electrode layers of LTPS TFT and Oxide TFT into a single shared gate electrode structure. The gate electrode is formed in the same layer for both transistor types, eliminating the need for separate gate electrode layers and reducing the total number of stacked film layers. This merging approach maintains the functional advantages of both transistor types while reducing stress mismatch and improving manufacturing yield.
Solution Approach 2:
The gate electrode layer serves a dual function by acting as the gate electrode for both LTPS TFT and Oxide TFT simultaneously. This multi-functional design allows a single film layer to fulfill the gating function for two different transistor types, reducing the overall layer count and simplifying the device structure while maintaining the complementary advantages of both transistor technologies.
2Adaptability or versatility
If additional film layers are added to support oxide transistor gate electrode, then oxide transistor functionality is achieved, but the risk of cracks and transistor failures increases due to excessive stacking
Solution Approach 1:
The patent combines the gate electrode functions into a single shared layer, eliminating the need for additional separate film layers that would introduce more interfaces and potential crack sites. The shared gate electrode structure reduces the total number of film-layer interfaces, thereby minimizing stress concentration points and reducing the risk of stress-induced cracks.
Solution Approach 2:
The patent applies different semiconductor layer materials (LTPS and oxide semiconductor layers) in different regions while sharing the same gate electrode layer. This local differentiation allows each transistor type to maintain its optimal material properties while avoiding the need for additional universal film layers that would increase overall device complexity and stress risk.
3Manufacturing precision
If separate gate electrode layers are used for LTPS TFT and Oxide TFT, then each transistor type can be optimized independently, but the manufacturing process complexity and number of film layers increase
Solution Approach 1:
The patent merges the gate electrode formation process into a single step that simultaneously creates the gate electrode for both LTPS TFT and Oxide TFT. This is achieved by forming the gate electrode layer once and using it for both transistor types, thereby reducing the number of deposition and patterning cycles while maintaining precise control over transistor characteristics through selective semiconductor layer processing.
Solution Approach 2:
The patent segments the semiconductor layer formation into distinct LTPS and oxide semiconductor layer processing steps, allowing independent optimization of each transistor type's active layer while sharing the gate electrode structure. This segmentation enables precise control over each transistor's electrical characteristics without requiring separate gate electrode layers, thus maintaining manufacturing precision while improving efficiency.
Data Source
AI summary
Disclosed are a display substrate, a manufacturing method thereof, a display panel and a display device. The display panel comprises: a base substrate provided with a first area and a second area which are not overlapped with each other; a low temperature poly-silicon transistor arranged in the first area, the low temperature poly-silicon transistor comprises a poly-silicon active layer; an oxide transistor arranged in the second area, the oxide transistor comprises a first gate electrode; the first gate electrode is arranged in a same layer as the poly-silicon active layer, and a material of the first gate electrode is heavily-doped poly-silicon.