Vertically Stacked Memory Structure With Shared Gates Over Logic
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving increased memory cell density, reduced footprint, and improved computing speed due to limitations in integrating memory structures with logic structures, leading to higher manufacturing costs and complexity.
Innovation Solution
The semiconductor device incorporates a memory structure with vertically stacked layers of memory cells and shared vias among multiple gate structures, allowing for increased memory cell density and reduced footprint, while enabling in-memory computing and near-memory computing by overlaying the memory structure over logic structures or interconnection layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory structures are integrated with logic structures using existing methods, then device functionality is achieved, but memory cell density is limited and footprint is large
Solution Approach 1:
The patent implements vertically stacked memory cells arranged in multiple layers above the logic structure, transitioning from planar two-dimensional layout to three-dimensional vertical stacking. This dimensional change allows significantly more memory cells to be packed into the same footprint area, directly resolving the contradiction between increasing memory cell density and reducing device footprint
2Quantity of substance
If memory structures are integrated with logic structures using existing methods, then device functionality is achieved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent combines memory cell formation with the existing logic structure fabrication process by using the logic structure's gate electrodes as shared control gates for the vertically stacked memory cells. This merging eliminates the need for separate, complex memory structure fabrication steps, thereby increasing memory cell density while avoiding proportional increases in manufacturing complexity
Solution Approach 2:
The logic structure's gate electrodes serve dual functions: controlling the logic transistors and controlling the memory cell channels. This multi-functionality allows the same structural elements to perform multiple roles, simplifying the overall device architecture and reducing manufacturing complexity while enabling high-density memory integration
3Speed
If memory structures are integrated with logic structures using existing methods, then device functionality is achieved, but computing speed is limited
Solution Approach 1:
The patent nests the memory cells within the vertical space above the logic structure, with memory cell channels positioned directly over the logic structure's gate electrodes. This nested arrangement minimizes the distance between memory and logic operations, enabling faster data access and computing speed while keeping the integration compact and manageable
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a memory structure including a first transistor channel, a gate structure overlying the first transistor channel, and a second transistor channel overlying the gate structure. The gate structure includes a control gate.