Shared-Gate Nanosheet Channel Structure With Thin Dielectric Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits (ICs) increases with smaller geometries, requiring innovative methods to enhance production efficiency and reduce costs.
Innovation Solution
The method involves forming a stack of semiconductor layers over a substrate, using alternating layers of different etch selectivity and oxidation rates, and employing advanced patterning and etching processes to create nanostructure transistors, such as nanosheet or FinFET structures, with precise control of dielectric and gate electrode layers to optimize channel regions and gate electrode sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent divides the gate electrode into multiple discrete gates (first gate, second gate, third gate) that can be independently formed and controlled. This segmentation allows for simplified processing of each individual gate while achieving complex overall device functionality, thereby reducing processing complexity despite smaller geometry sizes
Solution Approach 2:
The patent transitions from planar 2D transistor structures to three-dimensional FinFET and nanosheet structures with vertical channels. This dimensional change enables increased functional density and production efficiency by utilizing the third dimension for device stacking and integration, while the self-aligned formation processes maintain manufacturing simplicity
2Quantity of substance
If functional density is increased with smaller geometries, then more circuits fit per chip area, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures and spacer layers are formed first to define subsequent gate regions. These preliminary structures guide the formation of multiple gates with precise spacing and alignment, enabling high circuit density while maintaining ease of manufacture through self-aligned processes
Solution Approach 2:
The patent introduces intermediary spacer layers and mandrel structures that facilitate the formation of closely spaced gates. These intermediary elements act as templates and protective layers during manufacturing, enabling precise positioning of multiple circuits per chip area while simplifying the overall fabrication process through self-aligned formation
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.