Transistor Cell Layout Using Shared Gates for Ultra-Low PMOS Threshold
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current approaches to achieving ultra-low PMOS threshold voltage in integrated circuits face challenges such as work function metal tuning difficulties, dopant implantation causing mobility degradation, and dipole formation complications, which hinder the development of efficient computational devices for complex system modeling.
Innovation Solution
The implementation of a gate cut layout in transistor cells, where PMOS transistors without gate cuts experience increased strain, resulting in a lower threshold voltage, while NMOS transistors maintain suitable threshold and mobility levels, allowing for the design of ultra-low voltage transistor cells with improved circuit flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If work function metal tuning is used to achieve ultra-low PMOS threshold voltage, then PMOS threshold voltage is reduced, but filling narrow gate trenches becomes difficult
Solution Approach 1:
The patent changes the work function metal parameter to achieve ultra-low PMOS threshold voltage. By selecting specific work function metals with appropriate work function values, the patent reduces PMOS threshold voltage to ultra-low levels while maintaining manufacturability through standard trench filling processes.
2Manufacturing precision
If dopant implant is used to achieve ultra-low PMOS threshold voltage, then PMOS threshold voltage is reduced, but mobility degrades
Solution Approach 1:
The patent replaces the mechanical dopant implantation process with a work function metal-based approach. Instead of using physical dopant insertion that causes mobility degradation, the patent uses work function metal tuning to achieve the same threshold voltage reduction effect without the harmful side effects on carrier mobility.
3Manufacturing precision
If dipole formation is used to achieve ultra-low PMOS threshold voltage, then PMOS threshold voltage is reduced, but processing becomes complicated
Solution Approach 1:
The patent extracts and eliminates the complex dipole formation process from the manufacturing flow. By directly applying work function metal tuning, the patent achieves ultra-low PMOS threshold voltage without requiring the additional processing steps associated with dipole formation, thereby simplifying the overall manufacturing process.
4Manufacturing precision
If gate cut layout is used to achieve ultra-low PMOS threshold voltage with increased strain, then PMOS threshold voltage is reduced and PMOS mobility is increased, but NMOS mobility decreases
Solution Approach 1:
The patent applies local quality by implementing gate cut layout selectively for PMOS transistors while maintaining standard layouts for NMOS transistors. This localized approach allows the PMOS devices to benefit from increased strain and reduced threshold voltage, while NMOS devices maintain their optimal performance characteristics without unnecessary mobility degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the achievement of ultra-low PMOS threshold voltage with increased PMOS mobility and reduced NMOS mobility, providing enhanced computational efficiency and circuit design flexibility in integrated circuits.
Implementation Method 1
PMOS transistors without gate cuts experience increased strain, resulting in a lower threshold voltage
Data Source
Figure 1
Figure 2~3
Figure 4~6
AI summary
Integrated circuit dies, apparatuses, systems, and techniques, are described herein related to low and ultra-low threshold voltage transistor cells. A first transistor cell (191) includes separate semiconductor bodies contacted by separate gate electrodes having a dielectric material therebetween. A second transistor cell (192) includes separate semiconductor bodies contacted by a shared gate electrode that couples to both semiconductor bodies. Transistors of the second transistor cell may be operated at a lower threshold voltage than those of the first transistor cell due to increased strain on the semiconductor bodies from the shared gate electrode.