Shared-Gate CMOS Structure for Lower Parasitic SCR Leakage
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Solution Overview
Problem
Latchup phenomenon in CMOS circuits, triggered by internal or external noise, leads to malfunction or electrical failure, particularly in aerospace, outer space, server, and automobile applications, due to single event latchup caused by particle strikes or electromagnetic radiation.
Innovation Solution
The semiconductor device configuration includes specific active areas and gate arrangements, with certain regions coupled to metal contacts and others disconnected, forming equivalent SCR circuits that reduce the number of parasitic SCR paths and redirect current flow through lower resistance paths, thereby minimizing high current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors share gates in a CMOS circuit, then device complexity is reduced, but parasitic SCR paths increase causing latchup susceptibility
Solution Approach 1:
The shared gate structure is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can be independently controlled. This segmentation breaks the continuous parasitic SCR path into separate segments, preventing latchup propagation while maintaining the compact shared gate architecture for reduced device complexity.
Solution Approach 2:
An intermediate structure (such as an isolation region or dummy transistor) is introduced between the n-type and p-type transistor regions. This intermediary element acts as a barrier that interrupts the parasitic SCR current path, preventing latchup while allowing the gates to remain shared and reducing overall device complexity.
2Object-affected harmful factors
If parasitic SCR paths are reduced, then latchup resistance improves, but current leakage control becomes more challenging
Solution Approach 1:
Different regions of the semiconductor device are assigned different doping types and characteristics. Specifically, n-type regions are positioned adjacent to p-type regions in a controlled manner, creating localized areas with specific electrical properties. This local quality differentiation allows parasitic SCR paths to be interrupted in critical areas while maintaining proper current flow in active regions, thus improving latchup resistance without compromising current leakage control.
Solution Approach 2:
The doping concentration and type are varied across different regions of the device. By changing the electrical parameters (doping level, carrier concentration) in specific areas, the patent creates regions that are resistant to latchup while maintaining controlled current leakage characteristics in other regions, resolving the contradiction between latchup resistance and current leakage control.
Data Source
AI summary
A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.