Shared Gate Select Transistors for 3D Resistive Memory Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity and manufacturing challenges increase in high-density resistive memory cell arrays due to the need for a large number of select transistors, which complicates their arrangement and manufacturing process.
Innovation Solution
A semiconductor memory device design where select transistors share a single gate electrode, reducing the number of manufacturing processes and improving transistor stability by connecting them in a stacked configuration perpendicular to the substrate, with shared gate electrodes and symmetrical structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell array is highly densified to increase storage capacity, then the storage density is improved, but the number of select transistors increases which complicates the arrangement and manufacturing process
Solution Approach 1:
Multiple select transistors share a common gate electrode structure. Specifically, select transistors in different memory cell layers share the same gate electrode, reducing the total number of gate electrodes and simplifying the manufacturing process while maintaining high storage density
Solution Approach 2:
A single gate electrode structure serves multiple select transistors across different memory cell layers, making the gate electrode multi-functional. This universal structure reduces device complexity while supporting high-density storage
2Quantity of substance
If the number of select transistors is increased to support high-density memory cells, then the storage capacity is improved, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent merges the gate electrode structures of multiple select transistors into a single shared structure. This reduces the number of manufacturing steps required for gate electrode formation while still supporting the increased number of select transistors needed for high-capacity storage
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture where memory cell layers are vertically stacked. Select transistors in different layers share common gate electrodes, reducing manufacturing complexity despite increased storage capacity
Data Source
AI summary
A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode.