Shared-Gate Transistor Threshold Analysis for FinFET Defect Detection
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased complexity in manufacturing, resulting in high yield loss, reduced reliability of electrical interconnections, and low testing coverage due to difficulties in void-free filling of high aspect-ratio trenches during the fabrication process, particularly in FinFET, gate-all-around, and nanowire devices, where metal-depositing problems cause significant electrical failures that are hard to detect using routine wafer acceptance tests.
Innovation Solution
A method for analyzing semiconductor devices involving the application of a power-supply voltage to a shared gate electrode to turn on NMOS and PMOS transistors, measuring their threshold voltages, and plotting voltage offsets to detect electrical failures caused by metal-depositing issues, allowing for precise pinpointing of problematic gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the geometric size of semiconductor devices is decreased to increase functional density, then the number of interconnected devices per chip area is improved, but the manufacturing complexity increases and yield loss increases
Solution Approach 1:
The patent segments the gate electrode into multiple sections (first gate electrode section, second gate electrode section, third gate electrode section) with different widths. This segmentation allows each section to be optimized independently for its specific function, reducing overall manufacturing complexity while maintaining high functional density on the chip area.
Solution Approach 2:
Different sections of the gate electrode are designed with different local qualities (widths) to perform different functions. The first section has a wider width for stability, the second section has a reduced width for specific electrical characteristics, and the third section has yet another width for interconnection purposes. This local differentiation resolves the contradiction by allowing complex functionality without uniformly increasing manufacturing complexity.
2Area of moving object
If the geometric size of semiconductor devices is decreased to increase functional density, then the number of interconnected devices per chip area is improved, but yield loss increases
Solution Approach 1:
The patent incorporates a test structure (cut structure) during the preliminary fabrication stages that allows for early detection of manufacturing defects. By performing electrical measurements on this test structure before final device completion, potential yield losses can be identified and addressed early in the manufacturing process, preventing waste of subsequent processing steps.
Solution Approach 2:
The test structure provides feedback about the quality of metal deposition and gate electrode formation. By measuring electrical characteristics (such as resistance or threshold voltage) of the test structure, manufacturers can detect deviations from expected parameters and adjust processing conditions to maintain high yield, even as device dimensions are reduced.
3Ease of operation
If routine wafer acceptance tests are used to detect electrical failures, then testing simplicity is maintained, but testing coverage is insufficient to detect metal-depositing problems
Solution Approach 1:
The patent introduces a test structure as an intermediary element that mediates between the simple testing process and the complex metal-depositing problems. This test structure is specifically designed to be sensitive to metal deposition issues while maintaining simple electrical measurement procedures. It acts as a mediator that translates complex manufacturing quality issues into simple electrical measurements that can be performed with routine equipment.
Solution Approach 2:
The test structure is designed to automatically indicate metal-depositing problems through its electrical characteristics without requiring complex analysis or additional measurement steps. The structure itself provides the diagnostic information through standard electrical measurements, making the detection process self-service and maintaining testing simplicity while improving coverage.
Data Source
AI summary
The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (Vdd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (Vth) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (Vss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.