Shared Global Data Line Driving Unit for Stack Bank Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices with a stack bank structure, the large dimensions of the column control block due to separate data bus driving circuits for each bank hinder the reduction of circuit dimensions and increase the complexity of decoding circuits.
Innovation Solution
A common global data line driving unit is introduced to multiplex data from multiple local data buses corresponding to each bank, allowing shared data bus sensing and amplification circuits to reduce the overall size of the column control block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate data bus driving circuits are provided for each bank in a stack bank structure, then each bank can independently drive its data bus, but the column control block dimensions become large and circuit complexity increases
Solution Approach 1:
The patent merges the data bus driving circuits by providing a single shared driving circuit that serves multiple banks through multiplexing. The driving circuit includes a first driving unit for a first bank and a second driving unit for a second bank, both sharing common components such as the global data bus and control signals. This merging approach reduces the overall area of the column control block while maintaining the ability to drive data buses for multiple banks independently when needed.
Solution Approach 2:
The data bus driving circuit is designed with multi-functionality to serve multiple banks. The driving circuit can operate in different modes to drive data buses for the first bank, the second bank, or both simultaneously through multiplexed operation. This universal design allows a single driving circuit to replace what would traditionally require separate dedicated driving circuits for each bank, thereby reducing the column control block area.
2Reliability
If separate data bus driving circuits are provided for each bank, then data transmission reliability is improved, but decoding circuit complexity increases
Solution Approach 1:
The patent merges the driving circuits across banks, which consequently reduces the number of separate decoding circuits needed. The shared driving circuit uses common control signals and decoding logic that can be reused for different banks, thereby reducing the overall decoding circuit complexity while maintaining data transmission reliability through proper multiplexed control.
Solution Approach 2:
The driving circuit is designed with universal functionality to handle multiple banks through a single decoding path. The control signals are decoded once and then distributed to multiple driving units within the same circuit, eliminating the need for separate decoding circuits for each bank. This reduces decoding circuit complexity while preserving reliable data transmission through the multiplexed architecture.
Data Source
AI summary
A semiconductor memory device includes a plurality of banks a plurality of banks stacked in a column direction, a global data line corresponding to the plurality of banks and a common global data line driving unit for multiplexing data on a plurality of local data lines corresponding to each of the banks to transmit the multiplexed result to the global data line.