Shared Hash Table Architecture for Multi-Accelerator Data Compression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data compression accelerators face limitations in resource utilization due to area and logic resource requirements, which restrict the number of accelerators that can be incorporated onto a single chip, necessitating improved methods for reducing these constraints.
Innovation Solution
Implementing a shared hash table among multiple data compression accelerators, allowing simultaneous access and reducing resource utilization by partitioning the hash table dynamically or statically, thereby optimizing area and logic block usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data compression accelerators are implemented on a single chip, then compression throughput is improved, but area and logic resource requirements increase
Solution Approach 1:
Multiple data compression accelerators share a common hash table resource on the same chip, merging what would traditionally be separate resources into a shared pool that serves multiple accelerators simultaneously
Solution Approach 2:
The shared hash table is designed to serve multiple accelerator instances universally, allowing the same hardware resource to be dynamically allocated and accessed by different compressors based on operational needs
2Speed
If each data compression accelerator has its own dedicated hash table, then access speed is improved, but resource utilization efficiency decreases
Solution Approach 1:
Dedicated hash tables for each accelerator are merged into a single shared hash table resource that is collectively accessed by multiple accelerators, reducing total resource consumption while maintaining operational speed through parallel access mechanisms
3Quantity of substance
If a shared hash table is used by multiple accelerators, then resource utilization is improved, but access complexity increases
Solution Approach 1:
The shared hash table is segmented into multiple independent ports, allowing different accelerators to access different segments simultaneously, thereby reducing access conflicts and managing complexity through structured division
4Productivity
If more hash table ports are added for simultaneous access, then compression speed is improved, but area requirements increase
Solution Approach 1:
Instead of adding more hash table entries in the traditional dimension, the solution adds multiple access ports to the hash table, enabling parallel access paths that improve throughput without proportionally increasing the core hash table storage area
Data Source
AI summary
Methods, apparatus and design structures are provided for improving resource utilization by data compression accelerators. An exemplary apparatus for compressing data comprises a plurality of hardware data compression accelerators and a hash table shared by the plurality of hardware data compression accelerators. Each of the plurality of hardware data compression accelerators optionally comprises a first-in-first-out buffer that stores one or more input phrases. The hash table optionally records a location in the first-in-first-out buffers where a previous instance of an input phrase is stored. The plurality of hardware data compression accelerators can simultaneously access the hash table. For example, the hash table optionally comprises a plurality of input ports for simultaneous access of the hash table by the plurality of hardware data compression accelerators. A design structure for a data compression accelerator system is also disclosed.