Shared Instruction Stressing for Multi-Thread Hardware Validation
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Solution Overview
Problem
Current test generators for multi-thread systems are limited in generating shared test codes that can be executed concurrently or reused by multiple threads, leading to undetected hardware bugs and inefficiencies due to instruction-side testing challenges.
Innovation Solution
A technique for generating shared test codes that can be executed concurrently and repeatedly across threads, decoupling shared code generation from execution order, and allowing access at any physical address without thread-specific constraints, with features like thread-agnostic code generation, automatic memory allocation, and state preservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If constrained test generation is used to create valid tests from test templates, then test validity is improved, but testing completeness and bug detection capability deteriorate due to inability to generate shared test code for concurrent execution
Solution Approach 1:
The patent segments test code generation from test execution by introducing a shared memory address that stores test instructions accessible by multiple threads. The test generator creates test templates that are stored in shared memory, allowing concurrent threads to execute the same test instructions independently, thus enabling both valid constrained testing and comprehensive multi-threaded coverage.
Solution Approach 2:
The patent creates a universal test execution mechanism where a single shared memory address contains test instructions that can be accessed and executed by multiple threads simultaneously. This universal approach allows the same test code to serve multiple testing purposes across different threads, improving both testing completeness and bug detection capability while maintaining test validity.
2Ease of manufacture
If traditional test generation approaches are used, then simple test execution is achieved, but instruction-side testing becomes incomplete leading to undetected hardware bugs
Solution Approach 1:
The patent introduces shared memory as an intermediary between test generation and test execution. Test instructions are stored in this intermediary shared memory address, allowing multiple threads to access and execute the same test code concurrently. This intermediary mechanism enables comprehensive instruction-side testing while maintaining relatively simple test execution processes.
3Adaptability or versatility
If shared test code is generated for concurrent execution, then testing coverage is improved, but computational overhead increases
Solution Approach 1:
The patent uses memory copying rather than code duplication. Instead of creating multiple copies of test code for different threads, the system stores test instructions once in shared memory and allows multiple threads to reference and execute the same instructions. This approach improves testing coverage while minimizing computational overhead by avoiding redundant code generation and storage.
Data Source
AI summary
A computer-implemented method including: providing a test template for a hardware system-under-test comprising one or more execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by at least some of the one or more execution threads; generating and storing, at the predetermined shared memory address, a sequence of instructions which conform to the test template; building, based, at least in part, on the test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises at least generation and execution of a test; and executing the executable image of the hardware exerciser by at least a first execution thread of the one or more execution threads of the hardware system-under-test.