Shared Memory Interface Layout for Multi-HBM SoC Packaging
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Solution Overview
Problem
The integration of multiple high bandwidth memory (HBM) modules in System-on-Chip (SoC) circuits requires a larger periphery, increasing the size and cost of the SoC die, necessitating a solution that maintains compact size while enhancing memory capacity and reducing costs.
Innovation Solution
A system-on-chip (SoC) die is connected to multiple memory modules via a connection circuit on an interposer substrate, utilizing a buffer die with a shared memory interface to facilitate communication, allowing for additional memory modules without enlarging the SoC die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple HBM modules are integrated directly into the SoC die, then memory capacity and bandwidth are improved, but the SoC die size and manufacturing cost increase
Solution Approach 1:
The system separates the SoC die from the HBM modules by introducing an interposer substrate. The interposer acts as an independent intermediate platform that hosts the memory interfaces, allowing the SoC die to remain compact while supporting multiple HBM modules through the interposer's routing infrastructure.
Solution Approach 2:
The interposer substrate serves as an intermediary component between the SoC die and HBM modules. It provides the necessary memory interfaces and data path routing without requiring these interfaces to be physically located on the SoC die perimeter, thus enabling memory expansion without increasing SoC die area.
2Productivity
If multiple HBM modules are integrated directly into the SoC die, then memory bandwidth is improved, but manufacturing cost increases
Solution Approach 1:
The manufacturing process is segmented into separate steps for the SoC die and the interposer substrate. This allows each component to be manufactured and tested independently before final assembly, reducing the complexity and cost of manufacturing high-bandwidth memory systems compared to integrating everything into a single large SoC die.
Solution Approach 2:
The interposer substrate acts as a manufacturable intermediary that can be produced using standard semiconductor fabrication processes. It provides the high-bandwidth memory interfaces in a separate, cost-effective manner that does not require expensive customization of the SoC die itself.
3Adaptability or versatility
If memory interfaces are located at the periphery of the SoC die, then connection with memory modules is enabled, but the periphery area increases with more memory modules
Solution Approach 1:
The interposer substrate serves as an intermediary that relocates the memory interfaces from the SoC die periphery to the interposer itself. This allows the SoC die to maintain a compact size while the interposer provides the necessary peripheral connectivity for multiple HBM modules through its own routing infrastructure.
Solution Approach 2:
The system transitions from a two-dimensional layout where memory interfaces must be placed on the SoC die perimeter to a three-dimensional stacked architecture. The interposer substrate enables vertical stacking of HBM modules above the SoC die, allowing multiple memory interfaces to be supported without increasing the planar footprint of the SoC die.
Data Source
AI summary
A system includes a substrate comprising a first circuit. The system also includes an integrated circuit formed in a first die disposed on the substrate. The integrated circuit includes at least a processor, a controller, and a first memory interface. The first memory interface is located in a first edge of the first die and is configured to couple to the first circuit. The system also includes a first buffer circuit formed in a second die disposed on the interposer substrate adjacent to the first edge of the first die. The first buffer circuit includes a second memory interface configured to couple to the first connection circuit. The system further includes multiple memory modules disposed on the second die. Each of the multiple memory modules at least partially share the second memory interface to communicate with the integrated circuit.