Shared Interleaver Memory for Multi-Latency Transceivers
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Solution Overview
Problem
Implementing multiple latency paths in communication systems is challenging due to the high memory and processing power requirements of interleavers and coding blocks, which increase significantly with the number of paths, leading to inefficient resource utilization.
Innovation Solution
The solution involves sharing memory and processing resources between interleavers/deinterleavers and coders/decoders in a transceiver, allowing dynamic allocation based on application requirements such as data rate, latency, and bit error rate, and enabling configuration changes during initialization or user data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple latency paths are implemented in a transceiver to support different applications, then the system can satisfy different application requirements (video, voice, Internet access), but the memory and processing power requirements become larger
Solution Approach 1:
The patent merges multiple separate interleavers and coding blocks into shared memory resources. Instead of dedicating separate memory blocks to each latency path, the system combines them into a shared memory pool that serves multiple applications simultaneously, thereby reducing total memory requirements while maintaining support for video, voice, and Internet access applications
Solution Approach 2:
The patent creates universal shared memory resources that can be dynamically allocated to different latency paths based on application requirements. The shared memory pool can serve multiple functions - supporting video applications requiring low BER, voice applications requiring low latency, and Internet access applications with varying requirements - making the memory system multi-functional rather than dedicated to single applications
2Reliability
If separate memory blocks are allocated to each interleaver in multiple latency paths, then each application can have dedicated resources, but the overall memory consumption increases significantly
Solution Approach 1:
The patent combines separate memory blocks for different interleavers into a unified shared memory pool. This merging allows the system to maintain reliable resource allocation for each application while reducing total memory consumption through efficient shared access and dynamic allocation mechanisms
3Manufacturing precision
If dedicated coding blocks are implemented for each latency path, then coding performance can be optimized for specific applications, but processing power requirements increase
Solution Approach 1:
The patent merges multiple dedicated coding blocks into shared processing resources. By combining coding functionality across different latency paths, the system maintains optimized coding performance for various applications while reducing the total processing power required through resource sharing and dynamic allocation
Data Source
AI summary
A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.