Shared Interrupt Address Tables for Bus Node Capacity

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Solution Overview

Problem

The existing PCIe protocol's interrupt mechanism is limited by the storage capacity of the node device, which cannot accommodate a large quantity of interrupt events, leading to reduced service efficiency due to the use of aggregated interrupt events.

Innovation Solution

The proposed solution involves storing interrupt vectors and addresses separately in distinct tables, allowing multiple interrupt events to share a common address, thereby reducing storage requirements and supporting more interrupts within the given capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If interrupt data is stored in a single table with full duplication for each interrupt event, then each interrupt event can be independently addressed, but storage space is wasted and the capacity is limited

Engineering Contradiction:
Improvestorage capacity for interrupt eventsVSAvoidstorage space waste
Core Design Contradiction:
Quantity of substanceVSLoss of substance

Solution Approach 1:

The patent merges the storage of interrupt addresses by creating a shared interrupt address table that stores each unique interrupt address only once, rather than duplicating it in every interrupt event entry. This combining approach reduces storage space waste while maintaining the ability to address multiple interrupt events.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interrupt address table is designed to serve multiple interrupt events simultaneously. A single entry in the interrupt address table can be referenced by multiple interrupt event entries through the interrupt address field, making the storage structure universal and applicable to many interrupt events without duplication.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If interrupt addresses are shared among multiple interrupt events, then storage space is reduced, but the system must manage shared resources efficiently

Engineering Contradiction:
Improvenumber of supported interrupt eventsVSAvoidstorage structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the interrupt data structure into two separate tables: an interrupt vector table that stores interrupt vectors, and an interrupt address table that stores interrupt addresses. This segmentation allows independent management of each table and reduces the complexity of managing shared resources within a single monolithic structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interrupt address field acts as an intermediary that links interrupt events to the interrupt address table. Instead of directly embedding full interrupt address information in each interrupt event, the system uses this intermediary field to reference the shared interrupt address table, simplifying the management of shared resources.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250321911A1Interrupt reporting method and apparatus, and interrupt configuration method and apparatus
Publication Date: 2025.10.16 HUAWEI TECH CO LTD
  • US20250321911A1 patent drawing
  • US20250321911A1 patent drawing
  • US20250321911A1 patent drawing

AI summary

This application discloses an interrupt reporting method and apparatus, and an interrupt configuration method and apparatus. The interrupt reporting method is applied to a node device that performs communication through a bus system, and the node device includes an interrupt vector table and an interrupt address table. The method includes: obtaining an interrupt event (S710); generating an interrupt message of the interrupt event, where the interrupt message includes an interrupt vector and an interrupt address, the interrupt vector is obtained from the interrupt vector table, and the interrupt address is obtained from the interrupt address table (S720); and sending the interrupt message to a network node through the bus system (S730).