Shared Intra Transform Gates for Real-Time Video Encoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing video encoding technologies face challenges in achieving high-resolution real-time encoding without compromising video quality, often requiring lower quality or resolution due to hardware limitations in processing intra-predicted blocks.
Innovation Solution
Enhancing the hardware configuration of the intra feedback loop by using larger, shared gates and optimizing transform operations to process smaller transform units (TUs) more efficiently, allowing for increased throughput and faster processing of intra-predicted blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixel prediction from neighboring blocks is used to enhance video quality, then video quality is improved, but hardware encoder performance deteriorates due to increased processing complexity
Solution Approach 1:
The patent segments the intra prediction process by separating forward and inverse transforms into distinct stages, and further dividing the image into transform units (TUs) of various sizes. This segmentation allows parallel processing of different TU sizes using shared logic gates, improving throughput while maintaining prediction quality.
Solution Approach 2:
The patent implements shared logic gates that can handle multiple TU sizes (4x4, 8x8, 16x16, 32x32, 64x64) universally. The same logic gate infrastructure processes different TU sizes by accepting size as a parameter, eliminating the need for separate dedicated gates for each TU size and improving hardware efficiency.
2Manufacturing precision
If high-resolution encoding is performed, then video quality is improved, but processing time increases due to hardware limitations
Solution Approach 1:
The patent enables continuous processing of high-resolution images by implementing an efficient intra prediction loop with shared logic gates that can continuously process different TU sizes without interruption. The pipeline architecture maintains continuous data flow through the encoding process, reducing idle time and improving overall processing speed for high-resolution content.
3Measurement precision
If dedicated logic gates are used for each transform unit size, then processing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent replaces multiple dedicated logic gates with a single shared logic gate that can process different TU sizes. The shared gate receives TU size information and configures its operation accordingly, maintaining processing accuracy for each size while dramatically reducing hardware complexity and resource utilization.
Solution Approach 2:
The patent changes the operational parameters of the shared logic gate based on TU size input. By dynamically adjusting the gate's behavior according to the TU size parameter, the system maintains processing accuracy equivalent to dedicated gates while using a unified hardware structure.
Data Source
AI summary
This disclosure describes systems and methods for unrestricted intra content to improve video quality of real-time encoding. An example method may include receiving, at a logic gate included within an encoding pipeline of a video encoder, a first transform unit (TU) of a first size. The example method may also include receiving, at the logic gate, a second transform unit (TU) of a second size, wherein the first size and the second size are different. The example method may also include generating, using the logic gate, a first forward transform of the first TU and a second forward transform of the second TU.