Shared I/O Lines for Memory Subarrays

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Solution Overview

Problem

Current memory devices face inefficiencies in power consumption and data transfer due to the need for dedicated input/output lines for each subarray, which limits flexibility and increases power usage, especially in reduced page modes where only a subset of subarrays is activated.

Innovation Solution

Implementing input/output line sharing techniques that allow local I/O lines to be shared between multiple subarrays, enabling data transfer between subarrays and main I/O lines, and activating only necessary subarrays to reduce power consumption and enhance data transfer efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated input/output lines are used for each subarray, then data transfer reliability is improved, but power consumption increases and flexibility decreases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges I/O lines from multiple subarrays into shared I/O lines. Specifically, I/O lines from first and second subarrays are merged to form shared I/O lines that can be selectively coupled to either subarray, reducing the total number of I/O lines and associated power consumption while maintaining data transfer reliability through selective coupling.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic coupling mechanisms that allow I/O lines to be selectively connected to different subarrays based on operational needs. The coupling is not fixed but can be dynamically reconfigured, enabling the system to activate only necessary subarrays and their associated I/O lines, thereby reducing power consumption while maintaining reliability when needed.

Inventive Principle:
Principle #15Dynamics

2Speed

If dedicated input/output lines are used for each subarray, then data transfer speed is improved, but device complexity increases

Engineering Contradiction:
Improvedata transfer speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent combines I/O lines from multiple subarrays into shared resources, reducing the total number of I/O lines and simplifying the overall device structure. This merging reduces device complexity while maintaining data transfer speed through selective coupling that ensures dedicated pathways when required.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared I/O lines serve multiple functions by being selectively coupled to different subarrays. These universal I/O lines can handle data transfer for any activated subarray, reducing the need for dedicated lines for each subarray and thereby simplifying the device while maintaining performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If all subarrays are activated, then data transfer capacity is improved, but power consumption increases

Engineering Contradiction:
Improvedata transfer capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent enables dynamic activation and deactivation of subarrays based on data transfer requirements. When full data transfer capacity is needed, multiple subarrays can be activated; when lower capacity suffices, fewer subarrays are activated, reducing power consumption. The selective coupling mechanism allows this dynamic configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent allows activation of only the necessary subset of subarrays required for the current operation rather than activating all subarrays continuously. This partial action approach maintains adequate data transfer capacity for the specific task while significantly reducing power consumption by leaving unnecessary subarrays deactivated.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11830570B2Input/output line sharing for memory arrays
Publication Date: 2023.11.28 MICRON TECHNOLOGY INC
  • US11830570B2 patent drawing
  • US11830570B2 patent drawing
  • US11830570B2 patent drawing

AI summary

Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.