Shared Data Input Output Circuits in Semiconductor Memory Banks
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face difficulties in circuit and layout design due to the need for multiple signal lines and column control units for each small section, which becomes more complex as memory capacity and data processing speed increase, requiring a more efficient design to occupy the same or reduced area.
Innovation Solution
The semiconductor memory apparatus is designed with shared data input/output circuits and signal lines among small section pairs, reducing the number of local IO lines, column control units, and global IO lines, allowing data to be transmitted efficiently between pairs of small sections, thereby minimizing the circuit and layout complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each small section includes separate signal lines and column control units, then data transmission reliability is improved, but circuit complexity and area occupation increase
Solution Approach 1:
The patent merges signal lines and column control units to be shared among multiple small sections. Specifically, a single signal line serves multiple small sections, and column control units are shared resources that control multiple small sections, thereby reducing overall circuit complexity while maintaining functional reliability through coordinated access mechanisms.
Solution Approach 2:
The signal lines and column control units are designed with universal functionality to serve multiple small sections. The column control unit can selectively control different small sections based on control signals, and signal lines can carry data between multiple small sections, making these components multi-functional rather than dedicated to single sections.
2Quantity of substance
If the number of small sections is increased to expand memory capacity, then storage capacity is improved, but layout margin and design ease deteriorate
Solution Approach 1:
The patent employs universal column control units and signal lines that can serve multiple small sections. This multi-functionality allows the same control and signal infrastructure to support an increased number of small sections without proportionally increasing circuit complexity, thereby enabling expanded memory capacity while maintaining layout margin and design feasibility.
Solution Approach 2:
The memory bank is segmented into multiple small sections that can be independently addressed and controlled. This segmentation allows for scalable memory capacity expansion while using shared control resources, making the layout more manageable compared to a fully distributed architecture where each section has dedicated control circuits.
3Speed
If separate data input/output circuits are provided for each small section, then data access speed is improved, but area occupation and circuit complexity increase
Solution Approach 1:
The patent merges data input/output circuits into shared resources that serve multiple small sections. Instead of having separate I/O circuits for each small section, the design combines these functions into shared circuits that can be selectively accessed by different small sections through control signals, thereby reducing total circuit area while maintaining data access capability.
Solution Approach 2:
The patent introduces intermediary control mechanisms (column control units and control signals) that mediate access between multiple small sections and the shared data input/output circuits. This intermediary layer enables fast data access by selectively connecting specific small sections to the shared I/O circuits, maintaining speed performance while reducing area through resource sharing.
Data Source
AI summary
A semiconductor memory apparatus includes first and second data storing/processing sections that have memory areas in a bank and the first and second data storing/processing sections share a circuit block that inputs and outputs the data, and a signal line that transmits the data.