Shared I/O Transceiver Clock Gating for RF Noise Isolation
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Solution Overview
Problem
The design of radio frequency integrated circuits (RFICs) for wireless mobile communications faces challenges in impedance matching and achieving low noise characteristics, particularly with the increasing demand for supporting higher frequencies and modulations like radio detecting and ranging (RADAR), leading to issues with signal noise interference between transmitters and receivers.
Innovation Solution
A transceiver and semiconductor chip design that incorporates a noise reduction circuit to control the activation and deactivation of signal transmission based on data enable signals, using a noise reduction control signal to manage the operation of mixers and switch circuits, thereby preventing noise from transmitters from affecting receivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the I/O port is shared by the first amplifier and the second amplifier to enable full-duplex operation, then communication efficiency is improved, but noise from the transmitter transfers to the receiver causing noise interference
Solution Approach 1:
The noise reduction circuit uses periodic clock signals (first clock signal and second clock signal) to control the switching between transmission and reception modes. By periodically activating the first mixer with the first clock signal during transmission intervals and the second mixer with the second clock signal during reception intervals, the system achieves time-division multiplexing that prevents noise transfer while maintaining full-duplex operational capability through the shared I/O port.
2Loss of energy
If the chip size of RFIC is reduced to lower package price, then manufacturing cost is improved, but impedance matching and noise characteristics become more difficult to achieve
Solution Approach 1:
The noise reduction circuit is divided into distinct functional segments: a first mixer for transmission signal generation, a second mixer for reception signal processing, and a noise reduction circuit that selectively activates these mixers based on operational mode. This segmentation allows independent optimization of each component's impedance characteristics while maintaining compact overall design, enabling precise impedance matching despite reduced chip size.
3Object-affected harmful factors
If the noise reduction circuit activates the first clock signal during activation time interval and deactivates it during deactivation time interval, then noise interference is reduced, but circuit complexity increases
Solution Approach 1:
The noise reduction circuit merges the clock signal generation and switching control functions into a single integrated circuit block. The first clock signal and second clock signal are generated and coordinated within the same noise reduction circuit, which simultaneously controls both the first mixer and second mixer operations. This merging approach reduces overall circuit complexity compared to having separate control circuits for each mixer while still achieving effective noise reduction through selective activation.
Data Source
AI summary
A transceiver includes a first mixer, a noise reduction circuit, a first amplifier, a second amplifier and an input/output (I/O) port. The first mixer receives first data and a first clock signal, and generates a first signal to be transmitted to an external device based on the first data and the first clock signal. The noise reduction circuit provides the first clock signal to the first mixer. The first amplifier amplifies the first signal received from the first mixer. The second amplifier amplifies a second signal received from the external device. The I/O port is shared by the first amplifier and the second amplifier, and is configured to output the amplified first signal and receive the second signal. The noise reduction circuit activates the first clock signal during an activation time interval for the first data, and deactivates the first clock signal during a deactivation time interval for the first data.