Shared-I/O Transceiver Timing for Low-Noise RF Reception
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Solution Overview
Problem
The design of radio frequency integrated circuits (RFICs) for wireless mobile communications faces challenges in impedance matching and achieving low noise characteristics, particularly with the increasing demand for supporting higher frequencies and modulations like radio detecting and ranging (RADAR), leading to issues with signal noise interference between transmitters and receivers.
Innovation Solution
A transceiver and semiconductor chip are designed with a noise reduction circuit that generates control signals in synchronization with data transmission, selectively activating or deactivating components like mixers and switch circuits to prevent noise transfer from the transmitter to the receiver, using shared I/O ports and incorporating low noise amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the I/O port is shared by the first amplifier and the second amplifier to reduce the number of components, then device complexity is reduced, but noise interference occurs when both transmit and receive operations are performed
Solution Approach 1:
The patent implements periodic action by controlling the first amplifier to operate only during transmission time intervals and the second amplifier to operate only during reception time intervals. The noise reduction circuit generates control signals that periodically enable/disable the amplifiers based on whether the transceiver is transmitting or receiving, thereby preventing noise interference while sharing the I/O port.
Solution Approach 2:
The patent applies dynamics by making the amplifier configurations dynamic rather than static. The noise reduction circuit dynamically adjusts the state of the first and second amplifiers based on real-time transmission/reception requirements. The control signals periodically change the operational state of the amplifiers, allowing the system to adapt between transmission and reception modes without physical isolation.
2Ease of manufacture
If the chip size is reduced to lower package price, then manufacturing cost is reduced, but impedance matching and noise characteristics become more difficult to achieve
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the operational parameters of the amplifiers through control signals. The noise reduction circuit modifies timing parameters, enable/disable states, and operational modes of the first and second amplifiers based on transmission/reception requirements. This allows precise control of signal characteristics despite the reduced chip size, maintaining good impedance matching and noise characteristics.
3Adaptability or versatility
If the operating frequency is increased to support 5G and RADAR modulations, then communication capability is improved, but noise interference between transmitter and receiver increases
Solution Approach 1:
The patent implements periodic action by synchronizing the operation of the first and second amplifiers with the transmission/reception time intervals. The noise reduction circuit generates control signals that periodically enable the first amplifier during transmission and the second amplifier during reception, preventing simultaneous operation that would cause noise interference. This timing-based control allows high-frequency operation for 5G and RADAR while maintaining low noise characteristics.
Data Source
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AI summary
A transceiver includes a first mixer, a noise reduction circuit, a first amplifier, a second amplifier and an input/output (I/O) port. The first mixer receives first data and a first clock signal, and generates a first signal to be transmitted to an external device based on the first data and the first clock signal. The noise reduction circuit provides the first clock signal to the first mixer. The first amplifier amplifies the first signal received from the first mixer. The second amplifier amplifies a second signal received from the external device. The I/O port is shared by the first amplifier and the second amplifier, and is configured to output the amplified first signal and receive the second signal. The noise reduction circuit activates the first clock signal during an activation time interval for the first data, and deactivates the first clock signal during a deactivation time interval for the first data.