Shared Last-Level Cache for CPU and Graphics Coherency

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Solution Overview

Problem

In computing systems, integrating multiple functional units like CPUs and graphics logic within the same platform leads to increased cache memory usage and power consumption due to differing cache coherency domains, resulting in performance degradation as these units often need to access slower main memory for information sharing.

Innovation Solution

Implementing a shared last-level cache (LLC) that includes information from both CPU and graphics logic caches, allowing data to be shared without accessing main memory, by copying graphics L1 cache contents to the mid-level cache and enabling CPU snooping of graphics mid-level cache, thus maintaining coherency across domains.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate cache hierarchies are maintained for CPU and graphics logic in different coherency domains, then each functional unit can operate independently with its own cache coherency protocol, but more cache memory is required and power consumption increases

Engineering Contradiction:

Improveindependence of cache coherency protocolsVSAvoidcache memory quantity

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent merges the CPU cache hierarchy and graphics logic cache hierarchy by having the graphics logic access the CPU's last-level cache (LLC) directly. This allows both functional units to share a common cache resource while maintaining their respective coherency protocols, thereby reducing the total cache memory required compared to completely separate hierarchies.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The last-level cache (LLC) serves multiple functions: it acts as the L2 cache for CPU cores and simultaneously serves as a shared cache for graphics logic. This multi-functional design allows the same cache structure to support both CPU and graphics operations, reducing overall memory requirements while maintaining protocol independence through domain-specific access interfaces.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If separate cache hierarchies are maintained for CPU and graphics logic, then each functional unit can operate independently, but system cost and power consumption increase

Engineering Contradiction:

Improveindependence of cache coherency protocolsVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

By merging the cache hierarchies so that graphics logic can access the CPU's LLC directly, the patent eliminates the need for a separate graphics cache hierarchy. This consolidation reduces the total power consumption associated with maintaining and operating multiple independent cache systems while preserving the ability of each functional unit to use its native coherency protocol through domain-specific interfaces.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If information is shared among different functional units through main memory, then data can be accessed by both CPU and graphics logic, but access speed decreases due to main memory being slower than cache

Engineering Contradiction:

Improveinformation sharing capabilityVSAvoiddata access speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent introduces the CPU's last-level cache (LLC) as an intermediary between the CPU and graphics logic for data sharing. Instead of requiring direct main memory access for both functional units, the LLC serves as a high-speed buffer that both the CPU and graphics logic can access quickly. This intermediary cache structure enables fast information sharing while maintaining the independence of each functional unit's cache coherency domain.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Speed

If a shared last-level cache is implemented for both CPU and graphics logic, then information sharing speed improves by avoiding main memory access, but maintaining coherency across different coherency domains becomes more complex

Engineering Contradiction:

Improveinformation sharing speedVSAvoidcoherency maintenance complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the cache system into two coherency domains: a CPU coherency domain and a graphics coherency domain. Each domain maintains its own coherency protocols independently, while the last-level cache serves as a shared resource. This segmentation allows the system to achieve fast information sharing through the shared LLC while managing coherency complexity by keeping the domains separate and using domain-specific access interfaces.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10204051B2Technique to share information among different cache coherency domains

Publication Date: 2019.02.12 META PLATFORMS INC

AI summary

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.