Shared Redundancy Latch Decoder for DRAM Area Reduction
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Solution Overview
Problem
In the manufacturing of dynamic random access memory (DRAM) or pseudo SRAM, memory cells in the row or column direction may be defective, leading to inefficiencies in redundancy resource utilization and circuit area waste due to unused latch resources in redundancy latch sections.
Innovation Solution
A redundancy latch decoder circuit is introduced, where redundancy latch sections are configured into sharing groups, allowing shared redundancy latch units to be utilized by multiple memory sections, thereby improving resource utilization and reducing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each memory section has dedicated redundancy latch sections, then each section can independently handle defects, but latch resources are wasted and circuit area increases
Solution Approach 1:
The patent makes latch units serve multiple functions by allowing them to be shared across different memory sections. Specifically, latch units in the first column redundancy latch section can serve both the first memory section and the second memory section, enabling one resource to perform multiple functions and eliminating the need for dedicated latch resources for each section.
Solution Approach 2:
The patent merges redundant latch resources across multiple memory sections by configuring the first and second column redundancy latch sections to share common latch units. This combining approach consolidates previously separate resources into a unified shared resource pool, reducing total circuit area while maintaining defect handling capabilities.
2Ease of manufacture
If redundancy latch sections are dedicated to individual memory sections, then defect replacement is straightforward, but resource utilization is low and area is wasted
Solution Approach 1:
The patent implements universality by configuring latch units to serve multiple memory sections. The first column redundancy latch section's latch units can latch addresses for defects in both the first and second memory sections, making the redundancy resources universal rather than section-specific, thereby improving utilization without complicating the defect replacement process.
3Device complexity
If unused latch resources remain in redundancy latch sections, then design is simple, but redundancy resource utilization decreases and area increases
Solution Approach 1:
The patent merges previously unused or underutilized latch resources across memory sections by establishing sharing relationships between the first and second column redundancy latch sections. This merging increases resource utilization without significantly increasing configuration complexity, as the sharing is achieved through systematic address latching across sections.
Data Source
AI summary
A redundancy latch decoder circuit is provided and includes: a redundancy latch circuit, including multiple redundancy latch sections corresponding to multiple memory sections of the memory, wherein each redundancy latch section includes at least one normal redundancy latch unit, at least a portion of the redundancy latch sections is configured into at least one redundancy latch sharing group, each redundancy latch sharing group includes at least one shared redundancy latch unit, each redundancy latch sharing group corresponds to at least two redundancy latch sections, and at least two redundancy latch sections share the at least one shared redundancy latch unit; and a redundancy decoder circuit, coupled to the redundancy latch circuit to receive a redundancy address, wherein the redundancy decoder circuit is configured to enable, in response to an addressing address matching the redundancy address, a corresponding redundancy signal line to address a redundancy memory resource in the memory.