Semiconductor Memory Shared-Latch Layout for Smaller Chips
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Solution Overview
Problem
There is a challenge in reducing the chip size of non-volatile memory devices, particularly in memory systems using NAND flash memory, without compromising performance.
Innovation Solution
The semiconductor memory device incorporates a configuration with two planes of memory cell arrays, each connected to a sense amplifier, and a shared latch circuit, reducing the need for duplicate latch circuits and optimizing the layout to minimize chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If duplicate latch circuits are provided for each plane, then each plane can operate independently, but the chip size increases
Solution Approach 1:
The patent merges the latch circuits by providing a first latch circuit that is shared between the first plane and second plane. This single latch circuit sequentially serves both planes, eliminating the need for duplicate latch circuits while maintaining the ability to operate each plane independently through sequential access control.
Solution Approach 2:
The first latch circuit is designed with multi-functionality to serve dual purposes: it latches data for the first plane during first time periods and latches data for the second plane during second time periods. This universal latch circuit replaces what would traditionally require two separate dedicated latch circuits, reducing chip area while preserving independent plane operation capability.
2Productivity
If separate latch circuits are used for each plane, then data can be latched simultaneously for multiple planes, but the manufacturing cost increases
Solution Approach 1:
By merging the latch circuit resources into a single shared first latch circuit, the patent reduces the total component count and manufacturing complexity. Although data latching occurs sequentially rather than simultaneously, the reduced bill of materials and simpler fabrication process lower manufacturing costs while maintaining adequate productivity for the memory system.
3Productivity
If more chips are produced per wafer, then manufacturing efficiency improves, but the chip size must be reduced
Solution Approach 1:
The patent merges latch circuit functionality across multiple planes, significantly reducing the peripheral circuit area on each chip. This area reduction enables more chips to be fabricated from a single wafer, improving manufacturing productivity and reducing the cost per chip while maintaining full functional capability of each memory chip.
Data Source
AI summary
A semiconductor memory device capable of reducing the chip size is provided. A semiconductor memory device includes first and second planes of memory cell arrays, first and second sense amplifiers connected to first and second bit lines connected to the first and second planes respectively. The semiconductor memory device further includes a latch circuit array connected to both the first and second sense amplifier and configured to store data to or from the first plane and data to or from the second plane.