Shared Latch Circuit for Memory Repair Address Storage
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Solution Overview
Problem
As memory device capacity increases with scaled-down process technology, the likelihood of memory cell failures grows, rendering devices inoperable and requiring efficient repair methods, such as redundancy memory cells and fuse circuits, to maintain yield and integration density.
Innovation Solution
The implementation of a shared latch circuit in memory devices for storing addresses and information, which allows for multi-purpose use during test and normal operations, enabling efficient detection and programming of repair addresses without increasing the device's area, by using test determining and control signal generation circuits to manage latch signals and fuse programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity of the memory device is increased while process technology is scaled down, then the integration density and speed of each device are improved, but the possibility of memory cell failures increases
Solution Approach 1:
The patent divides the memory device into functional segments: normal memory cells and redundancy memory cells. When a failure occurs in normal memory cells, the system segments the address space to redirect accesses to redundancy memory cells, thereby maintaining overall device reliability while preserving high capacity
Solution Approach 2:
The patent changes the operational parameters of the memory device by dynamically adjusting address translation through the fuse circuit and latch circuit. When failures are detected, the system modifies address mapping parameters to bypass failed cells and redirect to redundant cells, maintaining reliability without sacrificing capacity
2Reliability
If redundancy memory cells and fuse circuits are used to repair failed memory cells, then the yield and integration density are maintained, but the device area increases
Solution Approach 1:
The latch circuit is designed to serve multiple functions: it stores repair addresses during test mode and normal operating addresses during regular operation. This multi-functionality eliminates the need for separate dedicated repair address storage circuits, thereby maintaining reliability through redundancy while avoiding additional area overhead
Solution Approach 2:
The patent merges the test mode address storage function and normal operation address storage function into a single latch circuit. By combining these functions and using a single fuse circuit for address translation in both modes, the system maintains high yield through repair capabilities without increasing the overall device area
3Productivity
If a latch circuit is dedicated to storing repair addresses during test mode, then the detection and programming of repair addresses is efficient, but the storage capacity for normal operation is reduced
Solution Approach 1:
The latch circuit is designed to dynamically switch between storing repair addresses during test mode and storing normal operating addresses during regular operation. This dynamic reconfiguration allows the same hardware resource to serve both repair efficiency and storage capacity requirements at different operational stages, maximizing both productivity and quantity without compromise
Data Source
AI summary
A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.