Shared Data Transfer Latches for Multi-Plane Non-Volatile Memory
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in efficiently utilizing space on memory dies due to the need for dedicated data transfer latches, which limits the area available for peripheral circuitry and restricts the implementation of additional functionalities.
Innovation Solution
Implementing a shared data transfer latch architecture, where two planes share a common data transfer latch, allowing dynamic data latches in each plane, thereby optimizing space usage and enabling more efficient operations such as read and program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated data transfer latches are implemented for each plane, then data transfer reliability is improved, but area efficiency deteriorates
Solution Approach 1:
The patent merges the data transfer latch resources between two planes by implementing a shared latch structure. The first and second planes share a common data transfer latch that can be dynamically allocated to either plane based on operational needs, thereby reducing the total latch count while maintaining data transfer reliability through coordinated control mechanisms.
Solution Approach 2:
The shared data transfer latch is designed to serve multiple functions by being accessible to both planes. The latch structure incorporates control logic that enables it to function as a data transfer latch for plane 0 during certain operations and for plane 1 during other operations, making a single component perform the role of what would traditionally require two separate components.
2Speed
If dedicated data transfer latches are implemented for each plane, then data transfer speed is improved, but area efficiency deteriorates
Solution Approach 1:
The patent implements dynamic control of the shared data transfer latch through time-multiplexed operation. The control logic dynamically allocates the shared latch to different planes based on which plane currently requires data transfer operations, enabling fast data transfer when needed while optimizing area usage through intelligent resource management rather than static dedicated assignments.
3Adaptability or versatility
If more latches are implemented, then functionality is improved, but area efficiency deteriorates
Solution Approach 1:
The shared latch architecture incorporates self-management capabilities through control logic that automatically determines which plane needs the latch resource and allocates it accordingly. This self-service mechanism eliminates the need for additional control circuitry that would otherwise be required to manage multiple dedicated latches, thereby maintaining functionality while improving area efficiency.
Data Source
AI summary
An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches. The shared transfer data latch can be used to transfer data for operations being performed on a first plane to use the data latches on the other plane for storing data for operations on the first plane.