Shared-Hardware LDPC Encoder for Multi-Code Parity Computation
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Solution Overview
Problem
The complexity of encoding Low Density Parity Check (LDPC) codes, particularly in reducing encoding complexity and hardware requirements for different block lengths and code rates, is a challenge due to the need for large memory storage and complex hardware implementation.
Innovation Solution
A parity check encoder design that computes intermediate and final parity bits using shared hardware resources, exploiting common sub-expressions among different codes to reduce storage and hardware complexity, allowing the same encoder hardware to support multiple block lengths and code rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If backward substitution is used to avoid inversion of the parity check sub-matrix, then encoding complexity is reduced, but parallelization introduces high complexity and large memory storage requirements
Solution Approach 1:
The parity check matrix H is partitioned into two sub-matrices H1 and H2, where H = [H1 H2]. This segmentation allows the encoding process to be divided into two stages: first computing intermediate parity bits using H1, then computing final parity bits using H2. This segmentation reduces the memory storage requirements compared to storing the entire matrix for backward substitution.
Solution Approach 2:
The first parity bits are computed in advance using the sub-matrix H1 before the final parity computation. This preliminary action allows the second parity computation to use only the necessary intermediate results rather than requiring storage of the entire parity check matrix, thereby reducing memory requirements while maintaining encoding efficiency.
2Device complexity
If the parity check matrix is partitioned into sub-matrices for encoding, then encoding complexity is reduced, but hardware requirements increase for supporting multiple codes
Solution Approach 1:
The encoder is designed with universal hardware resources that can be configured to support multiple different LDPC codes through parameter configuration rather than dedicated hardware for each code. The same encoder architecture can encode different codes by loading appropriate generator matrix parameters, making the hardware versatile and adaptable to various code requirements.
Solution Approach 2:
The encoder supports multiple codes by changing parameters such as the generator matrix G, sub-matrix partitions H1 and H2, and code length n, rather than requiring different hardware architectures. This parameter-based adaptability allows a single hardware implementation to efficiently support multiple LDPC codes with different block lengths and code rates.
3Reliability
If separate hardware resources are allocated for each code, then encoding accuracy is maintained, but hardware area and complexity increase
Solution Approach 1:
The encoder merges the computation of multiple codes into a single unified hardware architecture. By combining the parity computation logic and sharing common hardware resources (such as XOR gates, memory units, and control logic), the encoder maintains full encoding accuracy for all supported codes while significantly reducing the total hardware area compared to having separate dedicated hardware for each code.
Data Source
AI summary
The present invention is directed toward a parity check encoder for low density error correction codes and to an encoding method. In accordance with an embodiment, an encoder for error correction coding comprises: first hardware resources configured to receive a message bits vector and to compute an intermediate parity bits vector from the message bits vector wherein the intermediate parity bits vector is computed based on a sub-matrix of a parity check matrix; and second hardware resources configured to compute a parity bits vector from the intermediate parity bits vector, wherein the second hardware resources are configured to compute parity bits for multiple different codes, and wherein portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes.