Shared Level Shifter Control for Sense Amplifier Voltage Translation
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Solution Overview
Problem
Conventional semiconductor memory devices require multiple level shifters for each control signal, leading to increased space and power consumption due to the need for voltage level shifting across different regions, including peripheral and memory array areas.
Innovation Solution
Implementing shared level shifting circuits that provide voltage level translation for control signals across corresponding sections in a bank of the memory cell array, reducing the number of level shifter circuits and thus minimizing power consumption and chip space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple level shifters are provided for each control signal in each section, then voltage level translation is achieved for reliable sense amplifier operation, but chip space and power consumption increase
Solution Approach 1:
The patent merges level shifting functionality across multiple sections by providing a shared level shifter circuit that serves multiple sense amplifier sections. Instead of having dedicated level shifters in each section, the invention combines the level shifting function into a shared resource that can translate voltage levels for control signals across different sections, thereby reducing the total number of level shifters and chip space required.
Solution Approach 2:
The shared level shifter circuit is designed to perform multiple functions by serving multiple sense amplifier sections. This universal circuit can translate voltage levels for control signals that need to be applied to different sections, making a single circuit perform the work of multiple dedicated level shifters, thus reducing overall chip space while maintaining reliability.
2Reliability
If multiple level shifters are provided for each control signal in each section, then voltage level translation is achieved for reliable sense amplifier operation, but power consumption increases
Solution Approach 1:
The patent merges level shifting functionality across multiple sections by providing a shared level shifter circuit that serves multiple sense amplifier sections. Instead of having dedicated level shifters in each section, the invention combines the level shifting function into a shared resource that can translate voltage levels for control signals across different sections, thereby reducing the total number of level shifters and chip space required.
Solution Approach 2:
The shared level shifter circuit is designed to perform multiple functions by serving multiple sense amplifier sections. This universal circuit can translate voltage levels for control signals that need to be applied to different sections, making a single circuit perform the work of multiple dedicated level shifters, thus reducing overall power consumption while maintaining reliability.
3Reliability
If a level shifter is provided for each control signal of each section, then voltage level translation from peripheral region to memory array region is achieved, but device complexity increases
Solution Approach 1:
The patent merges level shifting functionality across multiple sections by providing a shared level shifter circuit that serves multiple sense amplifier sections. Instead of having dedicated level shifters in each section, the invention combines the level shifting function into a shared resource that can translate voltage levels for control signals across different sections, thereby reducing the total number of level shifters and chip space required.
Solution Approach 2:
The shared level shifter circuit is designed to perform multiple functions by serving multiple sense amplifier sections. This universal circuit can translate voltage levels for control signals that need to be applied to different sections, making a single circuit perform the work of multiple dedicated level shifters, thus reducing overall device complexity while maintaining voltage level translation accuracy.
Data Source
AI summary
Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.


