Shared Line Buffer Image Scaling Circuit for Dual-Display Interference
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Solution Overview
Problem
Conventional image scaling circuits require multiple sets of line buffer memories to scale images for dual-display panels with different resolutions, leading to increased costs and complex circuit layouts, with a high risk of interference.
Innovation Solution
An image scaling circuit architecture that integrates multiple scaling circuits to share a single line buffer memory, utilizing a line buffer control apparatus with vertical and horizontal scaling control units to perform interpolation operations for multiple scaling ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two sets of image scaling circuits are used to scale images for dual-display panels with different resolutions, then the image scaling function is achieved, but the cost increases and the circuit layout becomes more complex
Solution Approach 1:
The patent merges multiple image scaling circuits into a single integrated circuit that can perform multiple scaling operations simultaneously. The circuit includes a shared line buffer memory and multiple scaling units that can process different resolution requirements in parallel, eliminating the need for separate scaling circuits for each display panel.
Solution Approach 2:
The patent creates a universal image scaling circuit that can handle multiple scaling ratios and resolutions through a single device. The circuit incorporates configurable scaling units and control logic that can adapt to different display panel requirements, making one circuit perform the functions of multiple dedicated circuits.
2Adaptability or versatility
If two sets of image scaling circuits are disposed on a circuit board, then the dual-display function is achieved, but interference may occur easily
Solution Approach 1:
By merging multiple scaling circuits into one integrated unit, the patent reduces the physical separation between circuits while minimizing interference through shared resources and coordinated control. The single circuit architecture eliminates the electromagnetic interference that would occur between separate circuits operating in close proximity.
3Manufacturing precision
If two sets of line buffer memories are used in separate image scaling circuits, then the image registration is accurate, but the cost is undoubtedly increased
Solution Approach 1:
The patent combines multiple line buffer memories into a shared memory resource that serves multiple scaling circuits simultaneously. The memory is controlled by a unified control apparatus that manages data allocation and access for different scaling operations, reducing the total memory required while maintaining registration accuracy through coordinated control.
Solution Approach 2:
The patent introduces a line buffer control apparatus as an intermediary that manages the shared line buffer memory for multiple scaling circuits. This control apparatus coordinates memory access, ensures proper data allocation, and maintains image registration accuracy without requiring separate dedicated memories for each circuit.
Data Source
AI summary
An image scaling circuit and a method for scaling an image into images with different ratios are provided. The image scaling circuit includes a line buffer memory apparatus, a line buffer control apparatus, a first and a second scaling circuit. The first scaling circuit is coupled to the line buffer memory apparatus, and performs a first image scaling interpolation operation on the data output by the line buffer memory apparatus. The second scaling circuit is coupled to the line buffer memory apparatus, and performs a second image scaling interpolation operation on the data output by the line buffer memory apparatus. The line buffer control apparatus is coupled to the line buffer memory apparatus, the first scaling circuit and the second scaling circuit, for controlling the line buffer memory apparatus to receive or output a scan line data according to the operation status of the first and second scaling circuits.