Shared Load-Store Unit for Thread Switching in SIMD Processors
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Solution Overview
Problem
Current SIMD processor architectures face complexities due to separate local and shared memory systems, leading to performance overhead and programming challenges, particularly in inter-processor communication and memory access management.
Innovation Solution
A unified memory space is introduced, combining local and shared memory into a single address space, facilitated by a data packet-switched network that allows all processing elements to access memory seamlessly, hiding latency and enabling concurrent transactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate local and shared memory systems are used in SIMD processors, then each processing element has dedicated memory access, but programming complexity increases and performance overhead occurs due to explicit data movement requirements
Solution Approach 1:
The patent merges local memory and shared memory into a unified memory space that appears as a single address space to processing elements. This consolidation eliminates the need for separate memory management mechanisms and explicit data movement operations, thereby reducing programming complexity while maintaining efficient memory access through the unified addressable space.
2Adaptability or versatility
If data must be moved to shared memory or between PEs for sharing, then inter-PE communication is enabled, but performance overhead increases
Solution Approach 1:
The patent introduces a shared load-store unit as an intermediary component that manages all memory access operations. This unit handles data sharing between processing elements through a unified memory interface, eliminating the need for explicit data movement protocols and reducing the time overhead associated with inter-PE communication while maintaining full communication capability.
3Ease of operation
If complex cross-bar or multi-port memory systems are used to implement shared memory, then PEs can access shared memory, but device complexity and arbitration requirements increase
Solution Approach 1:
The patent implements a unified memory space that serves multiple functions: it acts as both local memory for individual processing elements and shared memory for inter-PE communication. This multi-functional memory system eliminates the need for complex cross-bar or multi-port structures, simplifying the overall memory system while maintaining ease of access for all processing elements through a single unified interface.
Data Source
AI summary
An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.