Shared Local Select Gate Drain Lines in 3D NAND Memory
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Solution Overview
Problem
The existing 3D NAND memory array architecture faces challenges in fitting into small pitches due to the large number of transistors required for routing local select gate drain lines, leading to reduced die yield and increased complexity.
Innovation Solution
The proposed solution involves sharing local select gate drain lines across multiple planes, where a single global select gate drives a plurality of planes, reducing the number of transistors needed and optimizing the layout within a small pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each plane has its own independent set of global word lines and global select gate drain lines, then each plane can be independently controlled, but the number of transistors required for routing increases significantly, reducing die yield and increasing complexity
Solution Approach 1:
The patent merges the global select gate drain lines across multiple planes by sharing a single global select gate drain line among several planes. This consolidation reduces the total number of transistors required for routing while maintaining the ability to independently control each plane through selective activation of local select gates and word lines.
Solution Approach 2:
The global select gate drain line is designed to serve multiple planes simultaneously, making it a universal resource. By enabling this single line to control select gates across different planes, the patent reduces routing complexity and transistor count while preserving independent plane control through selective local gate activation.
2Ease of operation
If local select gate drain lines are routed for each plane within a small pitch, then each plane can be addressed independently, but the routing of a large number of transistors in a relatively small space reduces die yield
Solution Approach 1:
The patent combines the routing of local select gate drain lines across multiple planes into shared pathways. Instead of dedicating separate routing resources to each plane, the same local select gate drain lines are shared among multiple planes, significantly reducing the number of transistors that must be routed within the small pitch area and thereby improving die yield.
Solution Approach 2:
The patent transitions from a two-dimensional routing approach to a three-dimensional architecture where vertical channels allow select gates to be stacked across multiple planes. This vertical stacking enables independent plane addressing while reducing the horizontal routing complexity and transistor count within the limited pitch space.
3Quantity of substance
If the pitch for vertical memory strings is only a few microns, then memory density is increased, but the number of transistors that can be routed in this small space is limited
Solution Approach 1:
The patent exploits the third dimension by stacking select gates and memory strings vertically across multiple planes. This vertical stacking within the narrow pitch enables high memory density while using shared local select gate drain lines to control multiple planes, thereby reducing the horizontal transistor routing capacity requirements.
Solution Approach 2:
The local select gate drain lines are designed as universal resources that can control select gates across multiple planes simultaneously. This multi-functionality allows the same physical routing infrastructure to serve multiple planes, reducing the overall transistor routing capacity needed within the constrained pitch while maintaining high memory density.
Data Source
AI summary
Memory devices, methods for accessing a memory cell, and memory systems are disclosed. One such memory device includes a plurality of planes of memory cells. Each plane of memory cells includes series strings of memory cells that each have a select gate drain transistor. Control gates of corresponding select gates are coupled together by a shared local control line. Each of a plurality of global control lines are coupled to their corresponding local control line with only a single global select gate.