Shared-Logic ECC Decoder for NAND Flash Error Correction
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Solution Overview
Problem
The reliability of NAND-type flash memory devices and other nonvolatile memory devices is compromised due to cell-to-cell interference and high error rates, necessitating effective error correction mechanisms, particularly in multi-level cell (MLC) and single level cell (SLC) structures.
Innovation Solution
An ECC decoder is designed with a finite state machine (FSM) controller and a shared logic circuit incorporating Galois field multipliers, XOR arithmetic elements, and multiplexers to perform syndrome, error location polynomial, and error correction operations, optimizing resource usage by sharing components across these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate logic components are used for each ECC operation (syndrome, error location polynomial, error location, error correction), then each operation can be performed independently and reliably, but the number of logic components and multipliers increases significantly, occupying most of the ECC decoder space
Solution Approach 1:
The patent implements a shared logic circuit where the same Galois field multipliers and XOR arithmetic elements are reused across all four ECC operations (syndrome operation, error location polynomial operation, error location operation, and error correction operation). Control signals direct the shared components to perform different functions at different times, eliminating the need for separate dedicated components for each operation while maintaining full operational capability and reliability
Solution Approach 2:
The patent merges previously separate logic circuits for syndrome calculation, error location polynomial generation, error location determination, and error correction into a single integrated shared logic circuit. This consolidation combines multiple functions into one unified structure, reducing the overall component count and decoder space occupation while preserving all necessary error correction capabilities
2Reliability
If multiple Galois field multipliers and XOR arithmetic elements are provided for each ECC operation, then sufficient computing resources are available for reliable error correction, but the logic components occupy most of the space in the ECC decoder
Solution Approach 1:
The patent makes the Galois field multipliers and XOR arithmetic elements universal by enabling them to serve all four ECC operations through time-multiplexed control. The same physical components are dynamically allocated to different operations based on control signals, providing sufficient computational resources for reliable error correction while occupying minimal decoder space
Solution Approach 2:
The patent combines multiple instances of Galois field multipliers and XOR arithmetic elements that would traditionally be dedicated to specific operations into a single shared pool of resources. This merging reduces the total area occupied by logic components in the ECC decoder while maintaining the computational capacity needed for robust error correction across all operation types
3Device complexity
If a shared logic circuit is used for all ECC operations, then the number of logic components and multipliers is reduced, but control signals are required to manage the sharing between different operations
Solution Approach 1:
The patent introduces control signals as intermediary elements that mediate between the various ECC operations and the shared logic circuit. These control signals act as intermediaries that direct the shared Galois field multipliers and XOR arithmetic elements to perform the appropriate operation at the appropriate time, enabling resource sharing while maintaining operational integrity without requiring complex manual management
Data Source
AI summary
An error correction code (ECC) decoder includes a finite state machine (FSM) controller and a shared logic circuit. The FSM controller generates a first control signal and a second control signal each corresponding to a certain state. The shared logic circuit includes a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation and an error correction operation, in response to the first and second control signals.