Shared Loop Filter PLLs for Smaller 3D Die Stacks
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Solution Overview
Problem
Existing three-dimensional integrated circuits (3DICs) face challenges due to the large die area occupied by individual phase-locked loops (PLLs) in each stacked die, which increases the total die area and limits functional capacity per volume unit.
Innovation Solution
Implementing a shared loop filter among PLLs in a die stack, where each PLL includes a phase and frequency detector, charge pump, voltage-controlled oscillator, and feedback divider, with a programmable connection element controlling the loop filter's ports to provide configurable bandwidth and enable phase locking with a reference clock, thereby reducing the size of each die and increasing functional capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each stacked die includes an individual PLL to generate individual clocks, then each die can have its own clock with varying frequencies, but the die area increases significantly
Solution Approach 1:
The patent merges the loop filter functionality across multiple PLLs by implementing a shared loop filter that serves multiple phase-locked loops in different stacked dies. This consolidation eliminates redundant loop filter circuits in each die, significantly reducing the total die area while maintaining the ability to generate individual clocks with varying frequencies for each die.
Solution Approach 2:
The shared loop filter is designed to serve multiple PLLs simultaneously, providing universal functionality across different dies. The loop filter can be dynamically configured to support different clock frequencies and phases for each die, enabling one component to perform multiple functions that would traditionally require separate dedicated components in each die.
2Ease of operation
If individual PLLs are implemented in each die, then each die has independent clock control, but the total die area and packaging complexity increase
Solution Approach 1:
The patent extracts the loop filter functionality from individual die implementations and relocates it to a shared resource that can be accessed by multiple PLLs. This separation allows each die to maintain independent clock control through its own PLL while the common loop filter is managed externally, reducing packaging complexity and inter-die connectivity requirements.
3Area of stationary object
If a shared loop filter is implemented among multiple PLLs, then die area is reduced, but the loop filter must serve multiple functions simultaneously
Solution Approach 1:
The shared loop filter incorporates dynamic configuration capabilities that allow it to adapt its parameters and behavior based on which PLL is currently active or what clock frequency is required. This dynamic reconfigurability enables the single loop filter to provide multiple functions and support different operating conditions without sacrificing adaptability.
Data Source
AI summary
An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop.