Shared MAC Hardware for Convolution Chaining
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Solution Overview
Problem
Current machine learning neural networks face inefficiencies in multiply-accumulate (MAC) computation due to the differing calculation methods between point-wise convolution (PWC) and depth-wise convolution (DWC) operations, leading to suboptimal utilization of MAC hardware and increased power consumption.
Innovation Solution
The solution involves sharing MAC hardware between PWC and DWC operations by swapping weight and activation inputs, utilizing a fixed adder tree structure, and chaining convolution operations to enhance utilization and reduce power consumption, while maintaining minimal structural changes and avoiding external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate MAC hardware is used for PWC and DWC operations, then each operation type can be optimized independently, but hardware utilization efficiency decreases and power consumption increases
Solution Approach 1:
The patent implements a universal MAC hardware structure that can perform both PWC and DWC operations by dynamically reconfiguring data flow paths and switching between different operational modes. The same MAC units are shared between convolution types through time-multiplexing and controlled data routing, eliminating the need for separate dedicated hardware for each operation type while maintaining full functionality for both PWC and DWC
Solution Approach 2:
The patent merges PWC and DWC operations into a single unified hardware pipeline by combining their data flow paths and sharing common MAC resources. The architecture integrates both operation types in a chained convolution structure where intermediate results are processed sequentially through shared MAC units, reducing overall hardware footprint and improving resource utilization
2Measurement precision
If dedicated MAC structure is used for DWC operations, then DWC calculation accuracy is maintained, but overall system power consumption increases
Solution Approach 1:
The MAC hardware is designed as a multi-functional unit that maintains precise DWC calculation capabilities while also supporting PWC operations. The same MAC units that perform accurate DWC computations are reused for PWC operations through dynamic reconfiguration, ensuring calculation accuracy is preserved while eliminating the need for separate dedicated hardware that would increase power consumption
3Productivity
If PWC operations are structured according to weights and activations bandwidth tradeoffs, then PWC efficiency is improved, but DWC operations become inefficient due to different calculation methods
Solution Approach 1:
The patent implements dynamic reconfiguration capabilities in the hardware architecture that allow the data flow paths and operational modes to be adjusted based on the type of convolution operation being performed. The system can dynamically switch between PWC-optimized modes and DWC-compatible modes, enabling the same hardware to efficiently handle both operation types despite their different calculation requirements and bandwidth characteristics
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that chains a plurality of convolution operations together, wherein the plurality of convolution operations include one or more one-dimensional (1D) convolution operations and one or more two-dimensional (2D) convolution operations, streams the plurality of convolution operations to shared multiply-accumulate (MAC) hardware, wherein to stream the plurality of convolution operations to the shared MAC hardware, the technology swaps weight inputs to the shared MAC hardware with activation inputs to the shared MAC hardware based on convolution type, and stores output data associated with the plurality of convolution operations to a local memory. Each of the 2D convolution operations may include a multi-cycle multiplication operation.