Shared MAC-PHY Circuit Data Chunk Processing for Switches
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Solution Overview
Problem
Current multi-port communication devices, such as switches, are costly, power-intensive, and inefficient due to their architecture, which struggles with managing large data packets and consuming significant ASIC die area.
Innovation Solution
A device with multiple MAC-PHY circuits connected to a shared interface, a shared memory unit, and layer-two processors, along with a DDR controller, processes data chunks efficiently by storing, processing, and transferring them through a large bus, performing protocol conversion, and applying Cyclic Redundancy Checks, thereby reducing the need for full-duplex processing and minimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If full-duplex multiple-port switches include a PHY layer circuit, a PHY-MAC circuit and a MAC layer circuit per port, then the device can manage multiple data flows effectively, but the device becomes costly and size consuming with high power consumption
Solution Approach 1:
The patent segments data packets into smaller data chunks that can be processed independently. Instead of processing entire packets through the full PHY-MAC layer stack simultaneously, the system divides packets into chunks that can be handled by shared resources, reducing the peak power consumption of per-port circuits while maintaining throughput capacity.
Solution Approach 2:
The patent merges multiple per-port PHY-MAC circuits into shared processing resources. Multiple ports share common MAC layer circuits and processing units, allowing the system to handle multiple data flows while using fewer physical circuits per port, thereby reducing overall power consumption and cost.
2Productivity
If full-duplex multiple-port switches include a PHY layer circuit, a PHY-MAC circuit and a MAC layer circuit per port, then the device can manage multiple data flows effectively, but the device consumes significant ASIC die area
Solution Approach 1:
By segmenting packets into chunks, the patent enables shared processing resources to handle multiple ports' worth of traffic. This reduces the need for dedicated PHY-MAC circuits at each port, thereby reducing the ASIC die area while maintaining the ability to manage multiple data flows through the shared processing architecture.
Solution Approach 2:
The patent implements universal shared MAC layer circuits and processing units that can serve multiple ports. These multi-functional resources replace numerous specialized per-port circuits, reducing the overall ASIC die area while maintaining full-duplex multi-port switching capability.
3Reliability
If the device processes entire data packets, then complete packet integrity is maintained, but traffic issues like starvation and overflow occur
Solution Approach 1:
The patent segments data packets into smaller chunks that can be processed and forwarded independently. This chunk-based processing prevents traffic starvation and overflow by allowing the system to interleave processing from multiple packets, ensuring fair resource allocation while maintaining packet integrity through proper reassembly at the destination.
Data Source
AI summary
In a scheme for processing data chunks, MAC-PHY circuits are adapted to store data chunks of large data packets and to provide same to a shared memory unit across an interface controlled by a controller. A data transfer monitor is adapted to monitor the progress of such data provision and shared layer-two processors perform data chunk processing operations and data packet processing operations based upon such progress. A double data rate (DDR) controller, coupled between the shared memory unit and a DDR memory unit, provides data chunks from the first shared memory unit to the DDR memory unit.