Shared Magnetization Fixed Layer for MRAM Cell Area Reduction
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Solution Overview
Problem
The existing magnetic domain wall motion type MRAM memory cell structure requires two transistors to control the write current, leading to increased memory cell area, which limits the degree of integration and efficiency.
Innovation Solution
A semiconductor device structure is introduced where each memory cell incorporates a single transistor and a common magnetization fixed layer shared between memory cells, reducing the number of transistors and bitlines, thereby minimizing the memory cell area by connecting one magnetization fixed layer to a common bitline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two transistors are used to control write current in each memory cell, then reliable data write is achieved, but memory cell area increases
Solution Approach 1:
The patent merges the write current control function from individual transistor-level control to bitline-level control. By using a common bitline to supply write current to multiple memory cells simultaneously, the need for separate transistors in each memory cell is eliminated, reducing memory cell area while maintaining write reliability through the shared bitline control mechanism
Solution Approach 2:
The common bitline serves multiple functions: it acts as both the write current supply path for multiple memory cells and the read current path. This multi-functionality eliminates the need for dedicated write control transistors in each memory cell, achieving area reduction while preserving the ability to reliably control write operations across multiple cells
2Ease of operation
If more transistors are used per memory cell, then better control of write current is achieved, but integration density decreases
Solution Approach 1:
The patent combines the write current control function at the bitline level rather than at the individual memory cell level. The common bitline provides unified control for write current distribution to multiple memory cells, achieving effective control while maximizing integration density by eliminating redundant transistor structures
Solution Approach 2:
The patent shifts the control dimension from vertical (individual cell-level transistors) to horizontal (shared bitline-level control). By moving the control function to the bitline interconnect layer, the patent achieves effective write current control without occupying additional area within each memory cell footprint, thereby improving integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the memory cell area, improving integration density and operational efficiency by eliminating the need for additional transistors and optimizing bitline intersections.
Implementation Method 1
Magnetoresistance effect elements having a magnetic tunnel junction (which may be referred to as 'MTJ', hereinafter) are often used as MRAM memory cells especially due to the advantage of a very large magnetoresistance effect
Implementation Method 2
A magnetic domain wall motion type MRAM achieves data write by moving the magnetic domain wall through the spin transfer effect of spin-polarized electrons with a write current flowing in the in-plane direction of a ferromagnetic film
Data Source
AI summary
A semiconductor device includes: a first memory cell, a second memory cell adjacent to the first memory cell, first and second write bitlines and a common bitline. The first memory cell includes: a first magnetization fixed layer, a first magnetic recording layer, a first reference layer, a first tunnel barrier film, and a first transistor. The second memory cell includes: a second magnetization fixed layer, a second magnetic recording layer, a second reference layer, a second tunnel barrier layer and a second transistor. Each of the first and second reference layer has a fixed magnetization. A common magnetization fixed layer having a fixed magnetization is coupled to the first and second magnetic recording layers. The common magnetization fixed layer and the common bitline is connected so that the common magnetization fixed layer and the common bitline are unable to be electrically unconnected.