Shared-Matrix CRC Circuit for DRAM Error Detection Overhead

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Solution Overview

Problem

As DRAMs shrink in size, bit errors in memory cells increase, leading to decreased yield and operational efficiency, necessitating effective error detection mechanisms in semiconductor memory devices.

Innovation Solution

An error detection code generation circuit incorporating a first and second CRC engine, along with an output selection engine, uses a shared generation matrix to generate and merge error detection code bits based on unit data and data bus inversion bits, enabling efficient error detection and correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM size is reduced to increase storage capacity, then storage density is improved, but bit error rate increases and manufacturing yield decreases

Engineering Contradiction:

Improvestorage densityVSAvoidbit error rate

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the data transmission into multiple lanes (first data lane and second data lane) with separate error detection codes for each lane. This segmentation allows independent error detection and correction for each lane, improving overall reliability without requiring a single large error detection code that would increase overhead.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of error detection code structure by using different code rates for different lanes (first code rate for first lane, second code rate for second lane). This allows optimization of error detection capability for each specific lane while maintaining overall system efficiency and addressing the reliability issue caused by miniaturization.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If error detection code length is increased to improve error detection capability, then reliability is improved, but data transmission efficiency decreases

Engineering Contradiction:

Improveerror detection capabilityVSAvoiddata transmission efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent divides the error detection code into multiple segments corresponding to different data lanes, with each segment having an appropriate code rate. This segmentation allows the system to achieve high error detection capability where needed while maintaining high transmission efficiency in other lanes, thus resolving the contradiction between reliability and productivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial error detection by using different code rates for different lanes based on their specific requirements. Rather than applying maximum error detection to all data uniformly, the system applies error detection selectively and proportionally to each lane, improving efficiency while maintaining necessary reliability.

Inventive Principle:

Principle #16Partial or excessive action

3Adaptability or versatility

If multiple CRC engines with different generation matrices are used to handle different code rates, then adaptability is improved, but device complexity increases

Engineering Contradiction:

Improvecode rate adaptabilityVSAvoidhardware overhead

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal CRC engine that can handle multiple code rates (first code rate and second code rate) through a single multi-functional device. This universal engine replaces the need for separate specialized CRC engines for each code rate, thereby maintaining code rate adaptability while significantly reducing device complexity and hardware overhead.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges multiple CRC engines with different generation matrices into a single unified CRC engine that can perform all required error detection functions. By combining these functions into one engine, the system maintains the ability to handle different code rates while reducing the overall complexity and resource consumption associated with having separate engines.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10868570B2Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same

Publication Date: 2020.12.15 SAMSUNG ELECTRONICS CO LTD

AI summary

An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.