Shared Memory Access Control for Secure Data Logging

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Solution Overview

Problem

Conventional information processing systems require increased memory size due to the need to replicate communication data in multiple memories during logging and routing operations across different operating systems or virtual machines, leading to inefficiencies and higher memory requirements.

Innovation Solution

An information processing device with a monitoring circuit that switches between non-secure and secure modes, utilizing a shared memory with a memory access control system to manage access permissions, allowing the non-secure processing unit to read and write in the shared memory while the secure processing unit reads from and writes to the shared memory and storage, respectively, without the need for redundant memory areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If communication data is replicated in multiple memories for logging and routing operations, then data accessibility and security are improved, but memory size requirements increase

Engineering Contradiction:
Improvedata accessibilityVSAvoidmemory size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges multiple memory spaces (secure and non-secure) into a single shared memory region. The communication data is stored once in shared memory at physical addresses, and both secure and non-secure processing circuits can access the same data through controlled memory access operations, eliminating the need for separate replicated memory areas.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared memory serves multiple functions simultaneously: it acts as both secure and non-secure memory space, supports both logging and routing operations, and provides data storage for multiple processing circuits. This multi-functionality is achieved through the memory access control mechanism that manages permissions dynamically.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If communication data is replicated in multiple memories for logging and routing operations, then data security between different operating systems is improved, but device complexity increases

Engineering Contradiction:
Improvedata securityVSAvoidmemory structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a memory access control circuit as an intermediary between processing circuits and the shared memory. This mediator manages all memory access requests, controls read/write permissions based on security attributes, and ensures that data security is maintained without requiring complex replicated memory structures. The control circuit interprets memory access control tables to enforce security policies.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If redundant memory areas are used for secure and non-secure processing, then access control and security are improved, but memory efficiency decreases

Engineering Contradiction:
Improveaccess controlVSAvoidmemory efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by assigning different security attributes and access permissions to different regions or portions of the shared memory. The memory access control table stores state information that specifies whether each memory region is locked or unlocked for non-secure processing circuits, allowing fine-grained control over access rights without requiring complete memory separation.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10545885B2Information processing device, information processing method, and computer program product
Publication Date: 2020.01.28 KK TOSHIBA
  • US10545885B2 patent drawing
  • US10545885B2 patent drawing
  • US10545885B2 patent drawing

AI summary

According to an embodiment, an information processing device includes a monitoring circuit, a non-secure processing circuit, a secure processing circuit, memory access control circuit. The monitoring circuit switches mode between a non-secure mode and a secure mode. The non-secure processing circuit runs in the non-secure mode, and reads communication data from and writes communication data in a shared memory. The secure processing circuit runs in the secure mode, and reads the communication data from the shared memory and writes the communication data in a storage. The memory access control circuit manages access from the non-secure processing circuit and the secure processing circuit based on a memory access control table in which physical addresses in the shared memory are associated with state information either indicating a locked state for not allowing writing but allowing reading by the non-secure processing circuit or indicating an unlocked state attained by cancelling the locked state.